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参数资料
| 型号： | CS6403-IL |
| 厂商： | CIRRUS LOGIC INC |
| 元件分类： | 编解码器 |
| 英文描述： | Echo-Cancelling Codec |
| 中文描述： | A/MU-LAW, PCM CODEC, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 32/54页 |
| 文件大小： | 761K |
| 代理商： | CS6403-IL |
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SMASTER - SCLK direction control, PIN 42Q, 4L
SMASTER is used in conjunction with other configuration-control pins to control operating
mode (see Tables 1 and 2). If SMASTER is high, the CS6403 is a timing master, meaning that
SCLK is an output, and the SCLK rate is set by the on-board crystal oscillator (nominally
2.048 MHz for an 8.192 MHz crystal). If SMASTER is low, the CS6403 is a timing slave,
meaning that SCLK is an input, and the SCLK rate is set by the external DSP, but
SCLK_RATE0 and SCLK_RATE1 must be set to reflect the nominal SCLK rate.
UALAW - PIN 13Q, 19L
When UALAW is high, 8-bit serial data is
μ
-law; when UALAW is low, 8-bit serial data is
A-law.
Serial Digital I/O
SCLK - Serial clock, PIN 8Q, 14L
SCLK is the bit clock for the serial interface. It may be an output operating at 2.048 MHz or
an input operating at 256 kHz, 1.024 MHz, or 2.048 MHz depending on the states of
SCLK_RATE0, SCLK_RATE1 and SMASTER.
SDI - Serial data in, PIN 7Q, 13L
SDI is the serial-data input to the CS6403.
SDO - Serial data out, PIN 6Q, 12L
SDO is the serial-data output from the CS6403.
SSYNC - Input synchronization signal for serial port, PIN 9Q, 15L
SSYNC is the serial-data synchronization strobe used when the CS6403 is a system-timing
slave. Should be grounded in master mode (SMASTER = 1).
SYNCOUT - Output synchronization signal for serial port, PIN 3Q, 9L
SYNCOUT is the serial-data synchronization strobe used when the CS6403 is a system-timing
master. Timing and duration depends on SFRAME.
Miscellaneous
CLK_SEL - PIN 15Q, 21L
Disable the on-chip phase-locked loop when high.
CLKIN - System input clock from external master, PIN 44Q, 6L
If the CS6403 is a system-timing master, a 8.192 MHz clock-crystal circuit is connected
between CLKIN and CLKOUT. If the CS6403 is a system-timing slave, CLKIN must be
grounded.
CLKOUT - System output clock, PIN 43Q, 5L
If the CS6403 is a system-timing master, a 8.192 MHz clock-crystal circuit is connected
between CLKIN and CLKOUT. Otherwise, CLKOUT is unconnected.
CS6403
32
DS192PP6
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相关代理商/技术参数 |
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|---|---|
| CS6403-IQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Echo-Cancelling Codec |
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