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参数资料
| 型号： | CS6403-IL |
| 厂商： | CIRRUS LOGIC INC |
| 元件分类： | 编解码器 |
| 英文描述： | Echo-Cancelling Codec |
| 中文描述： | A/MU-LAW, PCM CODEC, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 39/54页 |
| 文件大小： | 761K |
| 代理商： | CS6403-IL |
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Another important note about the differential
amplifier is that it is biased to swing around
1VDC. This is fine when the CS6403 gain stage
is on, as full scale into the part is 100mVpp.
When the gain stage is off, however, the full
scale input is 2Vpp, which forces the op-amp to
swing from 2V to 0V. Since the op-amp won’t
drive this close to the negative rail, it is advis-
able to change the bias point to about 2VDC.
This can be easily acheived by connecting pin 7
of the op-amp to the right side of R104, cutting
the trace above and below the right-hand pad of
R104, and strapping VCM to pin 5 of the op-
amp.
Far-End Analog Interface
In Mode 1 the far-end signals are provided to the
CS6403 via the MC145480 PCM codec by de-
fault. The analog signals provided to the
MC145480 are shown in Figure 3. The FE_IN
terminal block provides a differential input for
the far-end input. The fullscale voltage for this
input is 1.575Vp referenced to 2.4V in its cur-
rent unity gain configuration (see PCM Codec
below).
The FE_OUT terminal block provides the far-
end output either differentially or single-ended
depending on whether J8 or J10 is shorted. The
output level of each individual output is 1.575Vp
referenced about 2.4V. The FE_OUT is capable
of driving a 2k
load.
Signal polarity is indicated by "+" and "-" sym-
bols silkscreened near the connectors. These
connectors are not used in Mode 2.
CS6403
The CS6403 Echo Cancelling Codec, shown in
Figure 4, is the heart of the evaluation board.
See the CS6403 datasheet for full details on this
part.
The evaluation board is a good example of
proper layout and grounding of the CS6403.
Note that the part resides completely on the ana-
log ground plane and that all the power supplies
are decoupled with a 0.1
μ
F and 1
μ
F capacitor
with the smaller capacitor closest to the chip.
VCM are also well bypassed and test points exist
to monitor these values.
A test point labeled MICIN allows the evaluator
to monitor the signal at the MICIN pin of the
CS6403. This signal should be a maximum of
2Vpp with the internal gain stage off (GPIN3
high), and 100mVpp with the internal gain stage
on (GPIN3 low).
SPKROUTP and SPKROUTN also have test
points on either side of the screw terminal. J14
and J15 are provided so that intermediate cir-
cuitry can intercept and process the SPKROUT
signals, if desired. Note that SPKROUTP and
SPKROUTN each drive a maximum of 1.75Vpp
into an 8
load. Since they are 180 degrees out
of phase, this can be applied differentially to
produce 3.5Vpp. Do not ground either
SPKROUTP or SPKROUTN as this may damage
the speaker driver internally.
An 8.192MHz crystal is provided for Mode 1
applications. If the CS6403 is configured to op-
erate in Mode 2, the crystal should be removed
to prevent possible noise from interfering clocks.
The crystal is socketed to facilitate removal.
FE_OUT+
AGND
J8
J10
J3
FE_OUT-
J4
FE_IN+
FE_IN-
Figure 3. Far-End Input and Output
Analog Connections
CDB6403
DS192DB3
39
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PDF描述 |
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| CS6403-IQ | Echo-Cancelling Codec |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS6403-IQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Echo-Cancelling Codec |
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| CS6405AM | 制造商:Cypress Semiconductor 功能描述: |
| CS6410-000 | 制造商:TE Connectivity 功能描述:MT-LWA-.188-X-STK |
| CS6410AM | 制造商:Cypress Semiconductor 功能描述: |
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