参数资料
| 型号： | CS8952-IQZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 49/81页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 100/10 PHY 100TQFP |
| 标准包装： | 90 |
| 类型： | 收发器 |
| 规程： | MII |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 其它名称： | 598-1208 |
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CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
53
DS206F1
9MF Preamble
Enable
Read/Write 0
When set, this bit will force all management frames
(via MDIO, MDC) to be preceded by a 32 bit pream-
ble pattern of contiguous ones to be considered
valid. When cleared, it allows management frames
with or without the preamble pattern. The status of
this register is (inversely) reflected in the MF Pream-
ble bit in the Basic Mode Status Register (address
01h).
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
8
Fast Test
Read/Write 0
When set, internal timers are sped up significantly in
order to facilitate production test. Leave clear for
proper operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
7
CLK25 Disable
Read/Write When TCM pin is
low, reset to 1;
otherwise, reset to
0
Setting this bit will disable (tri-state) the CLK25 out-
put pin, reducing digital noise and power consump-
tion.
6
Enable LT/100
Read/Write 1
When set, normal link status checking is enabled.
When clear, this bit forces the link status to Link OK
(at 100 Mb/s), and will assert the LINK_OK LED.
5
CIM Disable
Read/Write Reset to the logic
inverse of the
value on the
REPEATER pin.
When set, this bit forces the Carrier Integrity Monitor
function to be disabled. When low, the Carrier Integ-
rity Monitor function is enabled, and detection of an
unstable link will disable the receive and transmit
functions.
4
Tx Disable
Read/Write 0
When set, this bit forces the 10 Mb/s and 100 Mb/s
outputs to be inactive. When clear, normal transmis-
sion is enabled.
If Tx Disable is set while a packet is being transmit-
ted, transmission is completed and no subsequent
packets are transmitted until Tx Disable is cleared
again. Also, if Tx Disable is cleared while TX_EN is
high, the transmitter will remain disabled until TX_EN
is deasserted. This prevents fragments from being
transmitted onto the network.
BIT
NAME
TYPE
RESET
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS8952-IQZR | 功能描述:以太网 IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| CS8952T | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-CQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQR | 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel |
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