参数资料
| 型号： | CS8952-IQZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 52/81页 |
| 文件大小： | 0K |
| 描述： | IC TXRX 100/10 PHY 100TQFP |
| 标准包装： | 90 |
| 类型： | 收发器 |
| 规程： | MII |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 其它名称： | 598-1208 |
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CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
56
DS206F1
8
PMD Loopback
Read/Write 0
When set, the scrambled NRZI transmit data is con-
nected directly to the NRZI receive port on the
descrambler. The loopback includes all of the
100BASE-TX functionality except for the MLT-3
encoding/decoding and the analog line-interface
blocks. When clear, the CS8952 is configured for
normal operation.
Note: Setting Remote Loopback and PMD Loopback
simultaneously will cause neither loopback mode to
be entered, and should not be done.
7
Strip Preamble
Read/Write 0
When set this bit causes the 7 bytes of MAC pream-
ble to be stripped off of incoming 100 Mb/s frames.
The data received across the MII will begin with the 1
byte Start of Frame Delimiter (SFD).
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
6
Alternate FDX CRS Read/Write 0
This bit changes the behavior of the CRS pin only in
the full-duplex (FDX) mode of operation. When set,
CRS will be asserted for transmit data only. When
clear, CRS will be asserted only for receive data.
5
Loopback Transmit
Disable
Read/Write 1
This bit controls whether loopback data is transmitted
onto the network. When set, any data transmitted
during PMD or ENDEC loopback mode will NOT be
transmitted onto the network. When clear, data will
be transmitted on the TX+/- pins as well as looped
back onto the MII pins.
4
Code Error Report
Select
Read/Write 0
When set, this bit causes code errors to be reported
by a value of 5h on RXD[3:0] and the assertion of
RX_ER.
When clear, this bit causes code errors to be
reported by a value of 6h on RXD[3:0] and the asser-
tion of RX_ER.
This bit is superseded by the Code Error Report
Enable bit.
3
Premature End
Error Report Select
Read/Write 0
When set, this bit causes premature end errors to be
reported by a value of 4h on RXD[3:0] and the asser-
tion of RX_ER.
When clear, this bit causes premature end errors to
be reported by a value of 6h on RXD[3:0] and the
assertion of RX_ER.
A premature end error is caused by the detection of
two IDLE symbols in the 100 Mb/s receive data
stream prior to the End of Stream Delimiter.
BIT
NAME
TYPE
RESET
DESCRIPTION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS8952-IQZR | 功能描述:以太网 IC IC 100BASE-TX and 10BASE-T Transceiver RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| CS8952T | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-CQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:100BASE E-X AND 10BASE-T TRANSCEIVER |
| CS8952T-IQR | 制造商:Cirrus Logic 功能描述:ETHERNET TXRX SGL CHIP 1-PORT 5V 10MBPS/100MBPS 100TQFP - Tape and Reel |
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