参数资料
型号: CS8952-IQZ
厂商: Cirrus Logic Inc
文件页数: 71/81页
文件大小: 0K
描述: IC TXRX 100/10 PHY 100TQFP
标准包装: 90
类型: 收发器
规程: MII
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 托盘
产品目录页面: 759 (CN2011-ZH PDF)
其它名称: 598-1208
CS8952
CrystalLAN 100BASE-X and 10BASE-T Transceiver
73
DS206F1
BP4B5B - Bypass 4B5B Coders. Input, Pin 56.
When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B decoder are
bypassed. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0].
The 4B5B Coders may also be bypassed under software control through bit 14 of the Loopback,
Bypass, and Receiver Error Mask Register (address 18h).
At power-up or at reset, the value on this pin is latched into bit 14 of the Loopback, Bypass and
Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 k
), or
the value may be set by an external 4.7 k
pull-up or pull-down resistor.
BPALIGN - Bypass Symbol Alignment. Input, Pin 52.
When driven high during power-up or reset, the following blocks are bypassed: 4B5B encoder, 5B4B
decoder, scrambler, descrambler, NRZI encoder, and NRZI decoder. Five-bit code groups are output and
input on pins RXD[4:0] and TXD[4:0]. The receiver will output five-bit data with no attempt to identify
code-group boundaries; therefore, the data in one RXD[4:0] word may contain data from two code
groups.
Symbol alignment may also be bypassed under software control through bit 12 of the Loopback,
Bypass, and Receiver Error Mask Register (address 18h).
At power-up or at reset, the value on this pin is latched into bit 12 of the Loopback, Bypass and
Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 k
), or
the value may be set by an external 4.7 k
pull-up or pull-down resistor.
BPSCR - Bypass Scrambler. Input, Pin 62.
When driven high during power-up or reset, the scrambler and descrambler is bypassed and NRZI FX
mode is selected.
The 100BASE-FX mode may also be entered under software control through bit 13 of the Loopback,
Bypass, and Receiver Error Mask Register (address 18h).
At power-up or at reset, the value on this pin is latched into bit 13 of the Loopback, Bypass and
Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 k
), or
the value may be set by an external 4.7 k
pull-up or pull-down resistor.
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