参数资料
型号: CY28548ZXC
厂商: Silicon Laboratories Inc
文件页数: 26/30页
文件大小: 0K
描述: IC CLK CK505 960M/965M 64TSSOP
标准包装: 28
类型: 时钟/频率发生器
PLL:
主要目的: Intel CPU 服务器
输入: 时钟
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 3:22
差分 - 输入:输出: 无/是
频率 - 最大: 400MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-TFSOP (0.240",6.10mm 宽)
供应商设备封装: 64-TSSOP
包装: 管件
CY28548
........................Document #: 001-08400 Rev ** Page 5 of 30
51
SRCT7/ CR#_F
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_F Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
52
VDD_SRC_IO
PWR
3.3V-1.25V Power supply for outputs.
53
SRCC8 / CPUC2_ITP
O, DIF Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
54
SRCT8 / CPUT2_ITP,
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
55
NC
No connect.
56
VDD_CPU_IO
PWR
3.3V-1.25V Power supply for outputs.
57
CPUC1
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
58
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
59
VSS_CPU
GND
Ground for outputs.
60
CPUC0
O, DIF Complement differential CPU clock outputs.
61
CPUT0
O, DIF True differential CPU clock outputs.
62
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
63
CKPWRGD / PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
64
FSB / TEST_MODE
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode.
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
QFN Pin Definitions (continued)
Pin No.
Name
Type
Description
TSSOP Pin Definitions
Pin No.
Name
Type
Description
1
PCI0 / CR#_A
I/O, SE 33 MHz clock/3.3V Clock Request # Input.
Selected via CR#_A_EN bit located in byte 5 bit 7.
The CR#_A_SEL bit in byte 5 bit 6 will select to control SRC0 or SRC2 when
asserted.
2
VDD_PCI
PWR
3.3V Power supply for PCI PLL.
3
PCI1 / CR#_B
I/O, SE 33 MHz Clock/3.3V Clock Request # Input.Selected via CR#_B_EN bit located
in byte 5 bit 5.
The CR#_B_SEL bit in byte 5 bit 4 will select to control SRC1 or SRC4 when
asserted.
4
PCI2 / TME
I/O, SE 33 MHz clock output / 3.3V-tolerance input for enabling trusted mode
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
5PCI3
O, SE 33 MHz clock output
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