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参数资料
| 型号： | CY38015V144-66BBC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, 18.9 ns, PBGA144 |
| 封装： | FBGA-144 |
| 文件页数： | 1/32页 |
| 文件大小： | 929K |
| 代理商： | CY38015V144-66BBC |
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CPLDs at ASIC Prices
Quantum38K ISR
CPLD Family
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03043 Rev. **
Revised April 20, 2001
Features
High density
— 15K to 100K usable gates
— 256 to 1536 macrocells
— 92 to 302 maximum I/O pins
— 8 Dedicated Inputs including 4 clock pins and 4
global control signal pins; 4 JTAG interface pins for
reconfigurability
Embedded Memory
— 8K to 48K bits embedded dual-port Channel memory
83 MHz in-system operation
AnyVolt interface
— 3.3V and 2.5V VCC operation
— 3.3V, 2.5V and 1.8V I/O capability
Low Power Operation
— 0.18-
m 6-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
Simple timing model
— No penalty for using full 16 product terms / macrocell
— No delay for single product term steering or sharing
Flexible clocking
— 4 synchronous clocks per device
— Locally generated Product Term clock
— Clock polarity control at each register
Carry-chain logic for fast and efficient arithmetic oper-
ations
Multiple I/O standards supported:
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI
Compatible with NOBL, ZBT, and QDR SRAMs
Programmable slew rate control on each I/O pin
User-Programmable Bus Hold capability on each I/O
pin
Fully PCI compliant (as per PCI spec rev. 2.2)
Compact PCI hot swap compatible
Multiple package/pinout offering across all densities
— 144 to 484 pins in PQFP and FBGA packages
— Simplifies design migration across density
In-System Reprogrammable (ISR)
— JTAG-compliant on-board configuration
— Design changes don’t cause pinout changes
IEEE1149.1 JTAG boundary scan
Development Software
Warp
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows 95, 98 & NT for $99
— Supports all Cypress Programmable Logic Products
Note:
1.
Upper limit of typical gates is calculated by assuming only 50% of the channel memory is used.
2.
Standby ICC values are with no output load and stable inputs.
Quantum38K ISR CPLD Family Members
Device
Typical Gates[1]
Macrocells
Channel
memory
(Kbits)
Maximum
I/O Pins
fMAX2
(MHz)
Speed — tPD
Pin-to-Pin
(ns)
Standby ICC
TA=25°C
3.3/2.5V
38K15
8K–24K
256
8
134
83
15
10 mA
38K30
16K–48K
512
16
176
83
15
10 mA
38K50
23K–72K
768
24
218
83
15
10 mA
38K100
46K–144K
1536
48
302
83
15
10 mA
相关PDF资料 |
PDF描述 |
|---|---|
| CY38015V144-66BBI | LOADABLE PLD, 18.9 ns, PBGA144 |
| CY38015V144-83BBC | LOADABLE PLD, 15 ns, PBGA144 |
| CY38015V144-83BBI | LOADABLE PLD, 15 ns, PBGA144 |
| CY38015V208-66NC | LOADABLE PLD, 18.9 ns, PQFP208 |
| CY38015V208-66NI | LOADABLE PLD, 18.9 ns, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY38050V208-125NTC | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk |
| CY38050V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk |
| CY38050V208-83NTC | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk |
| CY38050V208-83NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk |
| CY38100V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk |
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