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参数资料
| 型号： | CY38015V144-66BBC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, 18.9 ns, PBGA144 |
| 封装： | FBGA-144 |
| 文件页数： | 29/32页 |
| 文件大小： | 929K |
| 代理商： | CY38015V144-66BBC |
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PRELIMINARY
Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. **
Page 6 of 32
Macrocell
Within each logic block there are 16 macrocells. Each
macrocell accepts a sum of up to 16 product terms from the
product term array. The sum of these 16 product terms can be
output in either registered or combinatorial mode. Figure 4
displays the block diagram of the macrocell. The register can
be asynchronously preset or asynchronously reset at the mac-
rocell level with the separate preset and reset product terms.
Each of these product terms features programmable polarity.
This allows the registers to be preset or reset based on an
AND expression or an OR expression.
An XOR gate in the Quantum38K macrocell allows for many
different types of equations to be realized. It can be used as a
polarity mux to implement the true or complement form of an
equation in the product term array or as a toggle to turn the D
flip-flop into a T flip-flop. The carry-chain input mux allows ad-
ditional flexibility for the implementation of different types of
logic. The macrocell can utilize the carry chain logic to imple-
ment adders, subtractors, magnitude comparators, parity tree,
or even generic XOR logic. The output of the macrocell is ei-
ther registered or combinatorial.
Carry Chain Logic
The Quantum38K macrocell features carry chain logic which
is used for fast and efficient implementation of arithmetic op-
erations. The carry logic connects macrocells in up to 4 logic
blocks for a total of 64 macrocells. Effective data path opera-
tions are implemented through the use of carry-in arithmetic,
which drives through the circuit quickly. Figure 4 shows that
the carry chain logic within the macrocell consists of two prod-
uct terms (CPT0 and CPT1) from the PTA and an input carry-
in for carry logic. The inputs to the carry chain mux are con-
nected directly to the product terms in the PTA. The output of
the carry chain mux generates the carry-out for the next mac-
rocell in the logic block as well as the local carry input that is
connected to an input of the XOR input mux. Carry-in and a
configuration bit are inputs to an AND gate. This AND gate
provides a method of segmenting the carry chain in any mac-
rocell in the logic block.
Macrocell Clocks
Clocking of the register is highly flexible. Four global synchro-
nous clocks (GCLK[3:0]) and a Product Term clock (PTCLK)
are available at each macrocell register. Furthermore, a clock
polarity mux within each macrocell allows the register to be
clocked on the rising or the falling edge (see macrocell dia-
gram in Figure 4).
PRESET/RESET Configurations
The macrocell register can be asynchronously preset and re-
set using the PRESET and RESET mux. Both signals are ac-
tive high and can be controlled by either of two Preset/Reset
product terms (PRC[1:0] in Figure 4) or GND. In situations
where the PRESET and RESET are active at the same time,
RESET takes priority over PRESET.
Figure 4. Quantum38K Macrocell
D
Q
PSET
RES
GCLK[3:0]
PTCLK
FROM PTM
CPT0
CPT1
P
R
C
[1:0]
0
1
0
1
To PIM
C
Carry Out
(to macrocell n+1)
Carry In
(from macrocell n-1)
Up To 16 PTs
PRESET
Mux
Clock
Polarity
Mux
RESET
Mux
Clock Mux
Carry Chain
Mux
XOR Input
Mux
Output Mux
Q
C
3
2
3
C
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| CY38015V144-66BBI | LOADABLE PLD, 18.9 ns, PBGA144 |
| CY38015V144-83BBC | LOADABLE PLD, 15 ns, PBGA144 |
| CY38015V144-83BBI | LOADABLE PLD, 15 ns, PBGA144 |
| CY38015V208-66NC | LOADABLE PLD, 18.9 ns, PQFP208 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY38050V208-125NTC | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk |
| CY38050V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk |
| CY38050V208-83NTC | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS COMM 0.18UM 2.5V/3.3V - Bulk |
| CY38050V208-83NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 72K GATES 768 MCRCLLS IND 0.18UM 2.5V/3.3V 2 - Bulk |
| CY38100V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk |
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