参数资料
型号: CY38015V144-66BBC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: PLD
英文描述: LOADABLE PLD, 18.9 ns, PBGA144
封装: FBGA-144
文件页数: 3/32页
文件大小: 929K
代理商: CY38015V144-66BBC
PRELIMINARY
Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. **
Page 11 of 32
IEEE 1149.1 Compliant JTAG Operation
The Quantum38K family has an IEEE 1149.1 JTAG interface
for both Boundary Scan and ISR operations.
Four dedicated pins are reserved on each device for use by
the Test Access Port (TAP).
Boundary Scan
The Quantum38K family supports Bypass, Sample/Preload,
Extest, Intest, Idcode and Usercode boundary scan instruc-
tions. The JTAG interface is shown in Figure 9.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Quantum38K family implements ISR by providing a IEEE
std 1149.1 JTAG compliant interface for on-board configura-
tion. Robust routing resources offer pinout flexibility and a sim-
ple timing model provides consistent system performance.
Configuration
Quantum38K is a SRAM based volatile device family that uses
Cypress’s CY3LV series of CPLD boot EEPROM to store con-
figuration data. Please refer to the data sheet titled “CPLD
Boot EEPROM” and the application note titled “Configuring
Delta39K/Quantum38K” for more details on configuration and
interface set-up between Quantum38K & CPLD boot PROM.
These documents can be found at http://www.cypress.com
For Quantum38K design, configuration is defined as the load-
ing of a user’s design into the volatile Quantum38K die. Pro-
gramming, on the other hand, is the loading of a user’s design
into the serial boot PROM.
Device configuration can begin in two ways. It can be initiated
by toggling the Reconfig pin from LOW to HIGH, or by issuing
the appropriate IEEE std 1149.1 JTAG instruction to the
Quantum38K device via the JTAG interface. There are two
IEEE std 1149.1 JTAG instructions that initiate configuration of
the Quantum38K. The Self Config instruction causes the
Quantum38K to (re)configure with data stored in the serial
boot PROM. The Load Config instruction causes the
Quantum38K to (re)configure according to data provided by
other sources such as a PC, automatic test equipment (ATE),
or an embedded micro-controller/processor via the JTAG
interface.
There are two configuration options available for issuing the
IEEE std 1149.1 JTAG instructions to the Quantum38K. The
first method is to use a PC with the C3 ISR programming cable
and software. With this method, the ISR pins of the
Quantum38K devices in the system are routed to a connector
at the edge of the printed circuit board. The C3 ISR program-
ming cable is then connected between the PC and this con-
nector. A simple configuration file instructs the ISR software of
the programming operations to be performed on the
Quantum38K devices in the system. The ISR software then
automatically completes all of the necessary data manipula-
tions required to accomplish configuration, reading, verifying,
and other ISR functions. For more information on the Cypress
ISR interface, see the ISR Programming Kit data sheet
(CY3900i).
The second configuration option for the Quantum38K is to uti-
lize the embedded controller or processor that already exists
in the system. The Quantum38K ISR software assists in this
method by converting the device HEX file into the ISR serial
stream that contains the ISR instruction information and the
addresses and data of locations to be configured. The embed-
ded controller then simply directs this ISR stream to the chain
of Quantum38K devices to complete the desired reconfigura-
tion or diagnostic operations. Contact your local sales office
for information on availability of this option.
Programming
There are multiple methods available for programming the se-
rial boot PROM. The first method uses Cypress’s CYDH2200E
CPLD Boot PROM Programming Kit to program via a two-wire
interface.
The second method is through third-party programmers. Pro-
gramming support for CY3LV series of boot PROMs is avail-
able on a wide variety of third-party programmers. All major
programmers (including BP Micro, Data I/O, System General,
Hi-Lo) support boot PROM programming.
Development Software Support
Warp
Warp is a state-of-the-art design environment for designing
with Cypress programmable logic. Warp utilizes a subset of
IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware De-
scription Language (HDL) for design entry. Warp accepts
VHDL or Verilog input, synthesizes and optimizes the entered
design, and outputs a configuration bitstream for the desired
Quantum38K device. For simulation, Warp provides a graphi-
cal waveform simulator as well as VHDL and Verilog Timing
Models.
VHDL and Verilog are open, powerful, non-proprietary Hard-
ware Description Languages (HDLs) that are standards for be-
havioral design entry and simulation. HDL allows designers to
learn a single language that is useful for all facets of the design
process.
Figure 9. JTAG Interface
Instruction Register
Boundary Scan
idcode
Usercode
ISR Prog.
Bypass Reg.
Data Registers
JTAG
TAP
CONTROLLER
TDO
TDI
TMS
TCLK
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CY38015V144-66BBI LOADABLE PLD, 18.9 ns, PBGA144
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