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参数资料
| 型号： | CY7C1487V25-133BGI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM |
| 中文描述： | 1M X 72 CACHE SRAM, 6.5 ns, PBGA209 |
| 封装： | 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 |
| 文件页数： | 21/30页 |
| 文件大小： | 1028K |
| 代理商： | CY7C1487V25-133BGI |
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CY7C1481V25
CY7C1483V25
CY7C1487V25
Document #: 38-05281 Rev. *H
Page 21 of 30
Notes
16.Timing reference level is 1.25V when V
= 2.5V and is 0.9V when V
= 1.8V.
17.Test conditions shown in (a) of
“AC Test Loads and Waveforms” on page 20
unless otherwise noted.
18.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially, before a read or write operation
can be initiated.
19.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of
“AC Test Loads and Waveforms” on page 20
. Transition is measured ± 200
mV from steady-state voltage.
20.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. The device is designed
to achieve High-Z before Low-Z under the same system conditions
21.This parameter is sampled and not 100% tested.
Switching Characteristics
Over the Operating Range
[16, 17]
Parameter
Description
133 MHz
100 MHz
Unit
Min
Max
Min
Max
t
POWER
Clock
V
DD
(Typical) to the first Access
[18]
1
1
ms
t
CYC
t
CH
t
CL
Output Times
Clock Cycle Time
7.5
10
ns
Clock HIGH
2.5
3.0
ns
Clock LOW
2.5
3.0
ns
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
Data Output Valid After CLK Rise
6.5
8.5
ns
Data Output Hold After CLK Rise
Clock to Low-Z
[19, 20, 21]
Clock to High-Z
[19, 20, 21]
2.5
2.5
ns
3.0
3.0
ns
3.8
4.5
ns
OE LOW to Output Valid
OE LOW to Output Low-Z
[19, 20, 21]
OE HIGH to Output High-Z
[19, 20, 21]
3.0
3.8
ns
0
0
ns
3.0
4.0
ns
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
Address Setup Before CLK Rise
1.5
1.5
ns
ADSP, ADSC Setup Before CLK Rise
1.5
1.5
ns
ADV Setup Before CLK Rise
1.5
1.5
ns
GW, BWE, BW
X
Setup Before CLK Rise
Data Input Setup Before CLK Rise
1.5
1.5
ns
1.5
1.5
ns
Chip Enable Setup
1.5
1.5
ns
t
AH
t
ADH
t
WEH
t
ADVH
t
DH
t
CEH
Address Hold After CLK Rise
0.5
0.5
ns
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
GW, BWE, BW
X
Hold After CLK Rise
ADV Hold After CLK Rise
0.5
0.5
ns
0.5
0.5
ns
Data Input Hold After CLK Rise
0.5
0.5
ns
Chip Enable Hold After CLK Rise
0.5
0.5
ns
[+] Feedback
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