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参数资料
| 型号： | DAC34SH84EVM |
| 厂商： | Texas Instruments |
| 文件页数： | 2/29页 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR DAC34SH84 |
| 标准包装： | 1 |
| DAC 的数量： | 4 |
| 位数： | 16 |
| 采样率（每秒）： | 1.5G |
| 数据接口： | LVDS |
| 设置时间： | 10ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | * |
| 其它名称： | 296-30857 DAC34SH84EVM-ND |
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Introduction
1
DAC34SH84 ................................................................................................................ 19
List of Tables
DAC348xEVM Jumpers: (make sure the following jumpers are at their default setting) ......................... 12
1
1.1
Introduction
Overview
This document is intended to serve as a basic user’s guide for the DAC3484/2 EVM Revision F, and
DAC34H84/SH84 EVM revision C and above.
The Texas Instruments DAC348x evaluation module (EVM) is a family of circuit boards that allows
designers to evaluate the performance of Texas Instruments' DAC348x family of digital-to-analog
converters (DAC). The 16-bit, ultra low power family of DACs has either 16-bit wide or 32-bit wide DDR
LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit NCO, on-chip PLL, and exceptional
linearity at high IFs. The EVM provides a flexible environment to test the DAC348x under a variety of
clock, data input, and IF output conditions.
DAC3484
DAC3482
DAC34H84
DAC34SH84
Output Channel
EVM Part No.
Maximum DAC Rate
Digital Interface
Maximum Data Rate per Channel
Maximum LVDS Bus Toggle Rate
4
DAC348x Rev. F
1.25GSPS
16-bit LVDS Interface
312.5MSPS
1.25GSPS
2
DAC348x Rev. F
1.25GSPS
16-bit LVDS Interface
625MSPS
1.25GSPS
4
DAC34H84 Rev. C
1.25GSPS
32-bit LVDS Interface
625MSPS
1.25GSPS
4
DAC34H84 Rev. C
1.5GSPS
32-bit LVDS Interface
750MSPS
1.5GSPS
TSW1400/TSW3100
Pattern Generator Support
TSW1400/TSW3100
TSW1400/TSW3100
TSW1400/TSW3100
with limited data rate
support
For ease of use as a complete IF transmit solution, the DAC348xEVM includes the Texas Instruments
CDCE62005 clock generator/jitter cleaner for clocking the DAC348x. Besides providing a high-quality, low
jitter DAC sampling clock to the DAC348x, the CDCE62005 also provides FPGA clocks to the
TSW1400EVM (or TSW3100EVM) as FPGA reference clocks.
The EVM can be used along with Texas Instruments TSW1400 or TSW3100 with limited data rate support
(up to 1.25GSPS LVDS Bus rate) to perform a wide varieties of test and measurements. The TSW1400
generates the test patterns that are fed to the DAC348x through a maximum 1.5 GSPS LVDS Bus port.
These EVM boards are also compatible with Altera ? and Xilinx ? FPGA development platforms for rapid
evaluation and prototyping. The on-board HSMC connector input allows direct connection to the HSMC
compatible Altera development platforms, and the externally attached FMC-DAC-Adapter board available
from TI enables the connection of the EVM to the Xilinx development platforms with FMC headers.
For evaluation of complete RF transmit solution, see the TSW308x EVM. The EVM integrates the
DAC348x, TRF3705, and LMK04800 devices into one RF transmitter system.
See the TSW308x EVM web folders at:
1.2
EVM Block Diagram
Figure 1 shows the configuration of the EVM with the TSW1400 or TSW3100 used for pattern generation.
2
DAC348x EVM
Copyright ? 2012, Texas Instruments Incorporated
SLAU432 – February 2012
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