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参数资料
| 型号： | DAC34SH84EVM |
| 厂商： | Texas Instruments |
| 文件页数： | 7/29页 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR DAC34SH84 |
| 标准包装： | 1 |
| DAC 的数量： | 4 |
| 位数： | 16 |
| 采样率（每秒）： | 1.5G |
| 数据接口： | LVDS |
| 设置时间： | 10ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | * |
| 其它名称： | 296-30857 DAC34SH84EVM-ND |
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Software Control
2.2.2
Digital Block Options
Figure 4. Digital Block Options
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Interpolation: allows control of the data rate versus DAC sampling rate ratio
(i.e. data rate x interpolation = DAC sampling rate).
Digital Mixer: allows control of the coarse mixer function.
Note: If fine mixer (NCO) is used, the “Enable Mixer” button must be checked, and the coarse
mixer must be bypassed. See the following NCO bullet for detail.
Inverse sinx/x filter: allows compensation of the sinx/x attenuation of the DAC output.
Note: If inverse sinx/x filter is used, the input data digital full-scale must be backed off
accordingly to avoid digital saturation.
Clock Receiver Sleep: allows the DAC clock receiver to be in sleep mode. The DAC has minimum
power consumption in this mode.
Clock Divider Sync: allows the synchronization of the internal divided-down clocks using either
FRAME, SYNC, or OSTR signal. Enable the divider sync as part of the initialization procedure or
resynchronization procedure.
Group Delay: allows adjustment of group delay for each I/Q channel. This is useful for wideband
sideband suppression. Note: This feature is not available for the DAC34SH84.
Offset Adjustment: allows adjustment of dc offset to minimize the LO feed-through of the modulator
output. This section requires syncing for proper operation. The synchronization options are listed
below:
– REGWR: auto-sync from SIF register write. If this option is chosen, the GUI automatically
synchronizes the offset adjustment with each value update by writing to 0x08 (offset A) or
0x0A (offset B) registers last.
– OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with
OSTR set as sync source
– SYNC: sync from the external LVDS SYNC signal.
– SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.
QMC Adjustment: allows adjustment of the gain and phase of the I/Q channel to minimize sideband
power of the modulator output.
– REGWR: auto-sync from SIF register write. If this option is chosen, the GUI automatically
synchronizes the offset adjustment with each value update by writing to 0x10 (QMC phase
AB) or 0x11 (QMC phase CD) registers last.
SLAU432 – February 2012
Copyright ? 2012, Texas Instruments Incorporated
DAC348x EVM
7
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