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参数资料
| 型号： | DAC34SH84EVM |
| 厂商： | Texas Instruments |
| 文件页数： | 8/29页 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR DAC34SH84 |
| 标准包装： | 1 |
| DAC 的数量： | 4 |
| 位数： | 16 |
| 采样率（每秒）： | 1.5G |
| 数据接口： | LVDS |
| 设置时间： | 10ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | * |
| 其它名称： | 296-30857 DAC34SH84EVM-ND |
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Software Control
– OSTR: sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with
OSTR set as sync source.
– SYNC: sync from the external LVDS SYNC signal.
– SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.
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NCO: allows fine mixing of the I/Q signal. The procedure to adjust the NCO mixing frequency are listed
below:
1. Enter the DAC sampling frequency in Fsample.
2. Enter the desired mixing frequency in both NCO freq_AB and NCO freq_CD .
3. Press Update freq
4. Sync the NCO block from the following options:
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REGWR: auto-sync from SIF register write. Writing to either Phase OffsetAB or Phase
OffsetCD can create a sync event.
OSTR : sync from the external LVPECL OSTR signal. Clock divider sync must be enabled with
OSTR set as sync source. Refer to the datasheet for OSTR period requirement.
SYNC : sync from the external SYNC signal
SIF SYNC: sync from SIF Sync. Uncheck and check the SIF Sync button for sync event.
2.2.3
Output Control Options
Figure 5. Output control Options
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Output Options: allows the configuration of reference, output polarity, and output delay
Data Routing: provides flexible routing of the A, B, C, and D digital path to the desired output channels.
Note: The DAC3482 does not support this mode.
DAC Gain: configures the full-scale DAC current and DAC3484/DAC3482 mode. With Rbiaj resistor set
at 1.28k Ω :
– DAC Gain = 15 for 30mA full-scale current.
– DAC Gain = 10 for 20mA full-scale current (default).
Output Shutoff On: allows outputs to shut-off when DACCLK GONE, DATACLK GONE, or FIFO
COLLISION alarm event occurs.
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DAC348x EVM
Copyright ? 2012, Texas Instruments Incorporated
SLAU432 – February 2012
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