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| 型号： | DAC34SH84EVM |
| 厂商： | Texas Instruments |
| 文件页数： | 5/29页 |
| 文件大小： | 0K |
| 描述： | EVAL MODULE FOR DAC34SH84 |
| 标准包装： | 1 |
| DAC 的数量： | 4 |
| 位数： | 16 |
| 采样率（每秒）： | 1.5G |
| 数据接口： | LVDS |
| 设置时间： | 10ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | * |
| 其它名称： | 296-30857 DAC34SH84EVM-ND |
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2.2.1.1
FIFO Settings
Software Control
The DAC348x has 8-samples deep FIFO to relax the timing requirement of a typical transmitter system.
The FIFO has an input pointer and an output pointer, and both pointers can accept various input sources
as reset triggers of input and output pointer position. One important application for input and output pointer
control is the ability to synchronize multiple DACs in the system. For additional information, see the
relevant DAC348x data sheet.
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2.2.1.2
FIFO Offset: The default position of FIFO output pointer after reset by the synchronization source. This
setting can be used to change the latency of the DAC348x.
Data Formatter Sync (DAC3482 and DAC3484): Synchronization source for FIFO data formatter.
Select between LVDS FRAME or LVDS SYNC signals.
FIFO Sync Select (DAC34H84 and DAC34SH84): Select the internal digital routing of LVDS ISTR or
LVDS SYNC to the FIFO ISTR path
FIFO Input Sync: Synchronization source for FIFO input pointer. Select among the LVDS FRAME
(ISTR), LVDS SYNC, and/or SPI register SIF-SYNC to reset the FIFO input pointer position.
FIFO Output Sync: Synchronization source for FIFO output pointer. Select among the LVDS FRAME
(ISTR), LVDS SYNC, SPI register SIF-SYNC, and/or OSTR signal to reset the FIFO output pointer
position.
– For single device application without the need for precise latency control, Single Sync Source Mode
may be used. The FIFO output pointer position can be reset with LVDS FRAME (ISTR), LVDS
SYNC, and/or SPI register SIF-SYNC. See the Single Sync Source Mode in the relevant DAC348x
data sheet for details.
– For multiple device synchronization, select the OSTR signal as the FIFO output synchronization
source. If the DAC is configured to accept external DAC Clock input, then the OSTR signal is the
external LVPECL signal to the OSTRP/N pins. If the DAC is configured to accept the internal on-
chip PLL clock, then the OSTR signal is the internally generated PFD frequency. See the Dual
Sync Sources Mode in the relevant DAC348x data sheet for details.
LVDS Delay Settings
Depending on the signal source implementation (i.e. TSW1400, TSW3100, or FPGA System), the
following options can be implemented to meet the minimum setup and hold time of DAC348x data
latching:
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Set the on-chip LVDS DATA or DATACLOCK delay: The DAC348x includes on-chip LVDS DATA or
DATACLK delay. The delay ranges from 0ps to 280ps with an approximate 40ps step. This LVDS
DATACLOCK delay does not account for additional PCB trace-to-trace delay variation, only the internal
DATACLK delay.
– The TSW1400 pattern generator sends out LVDS DATA and DATACLK as center aligned signal.
Additional DATACLK delay is not needed.
– The TSW3100 pattern generator sends out LVDS DATA and DATACLK as edge-aligned signal.
Typical setting of 160ps or more will help meet the timing requirement for most of the TSW3100 +
DAC348x EVM setup.
Modify the external LVDS DATACLK PCB trace delay: Additional trace length on the bottom side of the
PCB can be added to the LVDS DATACLK PCB trace length. Set SJP9, SJP10, SJP11, and SJP12 to
2-3 position for approximately 220ps of trace delay.
SLAU432 – February 2012
Copyright ? 2012, Texas Instruments Incorporated
DAC348x EVM
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