参数资料
型号: DAC34SH84EVM
厂商: Texas Instruments
文件页数: 9/29页
文件大小: 0K
描述: EVAL MODULE FOR DAC34SH84
标准包装: 1
DAC 的数量: 4
位数: 16
采样率(每秒): 1.5G
数据接口: LVDS
设置时间: 10ns
DAC 型: 电流
工作温度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: *
其它名称: 296-30857
DAC34SH84EVM-ND
Software Control
2.2.4
CDCE62005
Figure 6. CDCE62005 Tab Configured for 4x Interpolation
Clock frequency control is determined by register values in the CDCE62005 Control tab. See the
CDCE62005 data sheet for detailed explanations of the register configuration to change the clock
frequency.
The following CDCE62005 outputs are critical to proper operation of the DAC348x:
?
?
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Y A *: DAC348x DAC sampling clock. This clock is an ac coupled LVPECL. If the DAC348x is
configured for internal PLL mode, this will be the reference clock input for the PLL block.
– Y A * = Y1 for DAC3484 and DAC3482 EVMs
– Y A * = Y2 for DAC34H84 and DAC34SH84 EVMs
Y B *: DAC348x FIFO OSTR clock. This clock is an ac coupled LVPECL. The clock rate for this should
be at least F DAC /Interpolation/8 . See the DAC348x data sheet for more details.
– The whole OSTR clock equation needs to take account of both the Y1 CDCE62005 clock divider
ratio and the additional CDCP1803 divide-by-2 clock divider.
– This OSTR signal can be a slower periodic signal or a pulse depending on the application.
– Note: The FIFO OSTR clock should be disabled when the DAC348x is configured in PLL mode.
– Y B * = Y2 for DAC3484 and DAC3482 EVMs
– Y B * = Y1 for DAC34H84 and DAC34SH84 EVMs
Y3: FPGA Clock 1. This clock is an ac coupled LVDS. The clock rate for this should be
– F DAC /interpolation/2 for DAC3484
– F DAC /interpolation/4 for DAC3482, DAC34H84, and DAC34SH84
Y4: FPGA Clock 2. This clock is an ac coupled LVDS. This clock must be enabled when using the
DAC34H84 and DAC34SH84 with the TSW1400. The clock rate for this should be F DAC /interpolation/4
for DAC34H84, and DAC34SH84
SLAU432 – February 2012
Copyright ? 2012, Texas Instruments Incorporated
DAC348x EVM
9
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