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参数资料
| 型号： | DC1472A |
| 厂商： | Linear Technology |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO LTM4618 |
| 软件下载： | LTM4618 Spice Model |
| 设计资源： | DC1472A Design Files DC1472A Schematic |
| 标准包装： | 1 |
| 系列： | µModule® |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 1.2V，1.5V，1.8V，2.5V，3.3V，5V |
| 电流 - 输出： | 6A |
| 输入电压： | 4.5 ~ 26.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 500kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTM4618 |
| 相关产品： | LTM4618IV#PBF-ND - IC DC-DC UMODULE BUCK 6A 84-LGA LTM4618EV#PBF-ND - IC DC-DC UMODULE BUCK 6A 84-LGA |
| 其它名称： | DC1472 DC1472-ND |
LTM4618
PIN FUNCTIONS
NC (A1): No Connect. Leave ?oating.
FREQ (A2): Frequency Selection Pin. An internal low pass
?lter is tied to this pin. The frequency can be selected with
a voltage from this pin to SGND. A programming resistor
divider can be used to set the operating frequency. The
suggested operating frequency range is 400kHz to 780kHz.
Operating frequencies as low as 250kHz are possible af-
ter evaluating the inductor ripple current for the desired
con?guration. See the Applications Information section.
MODE/PLLIN (A3): Mode Selection or External Synchroni-
zation Pin. Tying this pin to INTV CC enables pulse-skipping
operation. Tying this pin low enables forced continuous
mode operation. Burst Mode operation is enabled by ?oat-
ing the pin. A clock on the pin will force the controller into
forced continuous mode of operation and synchronize to
the internal oscillator. The programming DC voltage has
to be removed for clock synchronization.
PGND (BANK 2: A4, B4, D4-D7, E1-E7, F1-F7, G1-G7,
H1-H7, J5-J7, K5, K7, L5-L7, M5-M7): Power ground
pins for both input and output returns.
V IN (BANK 1: A5-A7, B5-B7, C5-C7): Power Input Pins.
Apply input voltage between these pins and PGND pins.
Recommend placing input decoupling capacitance directly
between V IN pins and PGND pins.
TK/SS (B1): Output Voltage Tracking and Soft-Start Pin. An
internal soft-start current of 1.3μA charges the soft-start
capacitor. See the Applications Information section.
RUN (B2): Run Control Pin. A voltage above 1.35V on
7
BANK 1
V IN 6
this pin turns on the module. Forcing this pin below 1.1V
will shut down the output. The RUN pin has a 1μA pull-
up current source that increases to 10μA as the RUN pin
voltage reaches 1.5V and up to compliance. Therefore the
pin can be left ?oating for normal operation. A maximum
of 6V can be applied to the pin. A voltage divider can be
used for a UVLO function. See the Applications Informa-
tion section.
SGND (B3, C2 and C3): Signal Ground Pin. Return ground
path for all analog and low power circuitry. Tie a single
connection to PGND. See applications for details.
COMP (C1): Current control threshold and error ampli-
?er compensation point. The module has been internally
compensated for most I/O ranges.
EXTV CC (C4): External Voltage Input. Bypasses the internal
INTV CC LDO and powers the internal circuitry and MOSFET
drivers. If a 5V source is available, the internal LDO is
disabled, and the power dissipation is lower, especially at
higher input voltages. See the Applications Information
section.
V FB (D1): The negative input of the error ampli?er. Inter-
nally, this pin is connected to V OUT with a 60.4kΩ precision
resistor. Different output voltages can be programmed
with an additional resistor between V FB and SGND pins.
See applications for details.
PGOOD (D2): Output Voltage Power Good Indicator. Open-
drain logic output that is pulled to ground when the output
voltage is not within ±7.5% of the regulation point.
INTV CC (D3): Internal 5V Regulator Output. This pin is for
BANK 2
PGND
SW
5
SGND/PGND 4
CNTRL
3
2
1
BANK 3
V OUT
A
B
C
D
E
F
G
H
J
K
L
M
4618fa
7
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