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参数资料
| 型号： | DC746A |
| 厂商： | Linear Technology |
| 文件页数： | 10/36页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2412 |
| 软件下载： | QuikEval System |
| 设计资源： | DC746A Design File DC746A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2412 |
| 已供物品： | 板 |
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LTC2412
18
2412f
APPLICATIO S I FOR ATIO
WU
U
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. Data is shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. On the
32nd falling edge of SCK, the device begins a new conver-
sion. SDO goes HIGH (EOC = 1) indicating a conversion is
in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
32nd falling edge of SCK, see Figure 6. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 32 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
Figure 6. External Serial Clock, Reduced Data Output Length
SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSION
SLEEP
TEST EOC (OPTIONAL)
TEST EOC
DATA OUTPUT
Hi-Z
CONVERSION
2412 F06
MSB
SIG
CH0/CH1
BIT 8
BIT 27
BIT 9
BIT 28
BIT 29
BIT 30
EOC
BIT 31
BIT 0
EOC
Hi-Z
TEST EOC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
VCC
FO
REF+
SCK
CH1+
CH1–
SDO
GND
CS
114
2
3
13
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO VCC
CH0+
CH0–
4
5
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2412
3-WIRE
SPI INTERFACE
REF–
SLEEP
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