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参数资料
| 型号： | DK-NIOS-2S60N |
| 厂商： | Altera |
| 文件页数： | 31/56页 |
| 文件大小： | 0K |
| 描述： | NIOS II KIT W/STRATIX II EP2S60N |
| 标准包装： | 1 |
| 系列： | Stratix® II |
| 类型： | Nios?II |
| 适用于相关产品： | Stratix ll 2S60N |
| 所含物品： | 评估板，设计应用程序，软件，线缆和配件 |
| 相关产品： | 544-1906-ND - IC STRATIX II FPGA 60K 484-FBGA 544-1907-ND - IC STRATIX II FPGA 60K 484-FBGA 544-1908-ND - IC STRATIX II FPGA 60K 484-FBGA 544-1910-ND - IC STRATIX II FPGA 60K 484-FBGA 544-1912-ND - IC STRATIX II FPGA 60K 672-FBGA 544-1913-ND - IC STRATIX II FPGA 60K 672-FBGA 544-1914-ND - IC STRATIX II FPGA 60K 672-FBGA 544-1916-ND - IC STRATIX II FPGA 60K 672-FBGA 544-1915-ND - IC STRATIX II FPGA 60K 672-FBGA 544-1909-ND - IC STRATIX II FPGA 60K 484-FBGA 更多... |
| 其它名称： | 544-1697 |
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Board Components
Mictor
Connector (J25)
f
Altera Corporation
July 2005
The Mictor connector (J25) can be used to transmit up to 27 high-speed
I/O signals with very low noise via a shielded Mictor cable. J25 is used as
a debug port. Twenty five of the Mictor connector signals are used as data,
and two signals are used as clock input and clock output.
Most pins on J25 connect to I/O pins on the Stratix II device (U60). For
systems that do not use the Mictor connector for debugging the Nios II
processor, any on-chip signals can be routed to I/O pins and probed at J25
via a Mictor cable. External scopes and logic analyzers can connect to J25
and analyze a large number of signals simultaneously.
For details on Nios II debugging products that use the Mictor connector,
refer to www.altera.com .
Figure 2–12 shows an example of an in-target system analyzer ISA-
Nios/T (sold separately) by First Silicon Solutions (FS2) Inc. connected to
the Mictor connector. For details see www.fs2.com .
Figure 2–12. An ISA-Nios/T Connecting to the Mictor Connector (J25)
Five of the signals connect to both the JTAG pins on the Stratix II device
(U60), and the Stratix II device’s JTAG connector (J24). The JTAG signals
have special usage requirements. You cannot use J25 and J24 at the same
time.
Figure 2–13 below shows connections from the Mictor connector to the
Stratix II device. Figure 2–14 shows the pin out for J25. Unless otherwise
noted, labels indicate Stratix II device pin numbers.
2–23
Nios Development Board Reference Manual, Stratix II Edition
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