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| 型号： | DMA-MC-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | IP CORE MCDMA CTLR ORCA 4 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | DMAMCO4N2 |
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Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
Programming the MCDMA Controller
Programming the core to achieve the desired functionality is very similar in both the 8237 and non-8237 modes.
The differences lie in the address map and the name of the registers
For the 8237 mode, the steps to program the core are:
? Disable the controller through the command register
? Program the Mode Register
– Select the channel to be programmed
– Set the features on the channel to programmed, such as transfer mode, read/write/verify transfer, address
increment/decrement, etc.
? Write into the Address Registers and Word Count Register
– Set the base source address register
– Set the number of transfer to be performed in the Word Count Registers.
? Enable the controller
For the non-8237 mode, the steps to program the core are:
? Disable the controller
? Set Input ain
– The ?rst 3 bits of ain , ain[2:0] , selects which registered to be programmed. The rest of the bits select
which channel to be programmed.
? Program the Mode and Channel control registers of all the channels
? Write into the Address registers and Word Count register
? Enable the controller
The core remains in the idle state (SI) as long as DMA transfers are not requested. While in state SI, the dreq sig-
nals are sampled. When an unmasked DMA request is presented, the core enters the active state. The request can
be either a software or hardware request.
Although the internal registers can be programmed in state S0, or before the hlda signal is asserted, it is a good
practice to program the internal registers only while the core is in the Idle state (SI). The functionality of the control-
ler is not guaranteed to be deterministic if the internal registers are accessed during an active DMA cycle.
Reference Information
? ispLEVER Software User Manual , Lattice Semiconductor Corporation
? 8237A High Performance Programmable DMA Controller, Intel Corporation, September 1993.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DMA-MC-SC-N3 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DMA-MC-XM-N3 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DMA-MC-XP-N2 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DM-A-PP | 制造商:DDK 制造商全称:DDK Ltd. 功能描述:Conversion Connector |
| DMA-SG-E3-U1 | 功能描述:开发软件 DMA Scatter/Gather RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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