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| 型号： | DMA-MC-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IP CORE MCDMA CTLR ORCA 4 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | DMAMCO4N2 |
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Lattice Semiconductor
Table 2. State Descriptions (Continued)
Multi-Channel DMA Controller User’s Guide
State
Memory-to-Memory Read
Transfer State Three - S13
Memory-to-Memory Read
Transfer State Four - S14
Memory-to-Memory Write
Transfer State One - S21
Memory-to-Memory Write
Transfer State Two - S22
Memory-to-Memory Write
Transfer State Three - S23
Description
This is the third state of the memory-to-memory transfer. The state machine sam-
ples the ready signal and stays in this state as long as it is asserted. The machine
transitions to state S14 when the ready signal is de-asserted.
Input Signals: eopin_n , ready
Asserted Output Signals: memr_n , address
Possible State Transitions: S13, S14
This is the fourth stage of the memory-to-memory transfer. The state machine de-
asserts memr_n signal and asserts an enable signal to ?op the incoming data into
the temporary register. The state machine transitions to state S21, which is the ?rst
state of the memory-to-memory write transfer stage.
Input Signals: eopin_n
Asserted Output Signals: none
Possible State Transitions: S21
This is the ?fth stage of the memory-to-memory transfer mode. In the 8237 mode,
the content of the current address register on Channel 1 is put on the address bus.
In the non-8237 mode, the content of the destination address register on the chan-
nel being serviced is put on the address bus. The memr_n and memw_n signals are
de-asserted. The state machine transitions to state S22.
Input Signals: eopin_n
Asserted Output Signals: address
Possible State Transitions: S22
This is the ?fth state of memory-to-memory transfer. The state transitions to state
S23.
Input Signals: eopin_n
Asserted Output Signals: address
Possible State Transitions: S23
This is the seventh state of the memory-to-memory transfer. The memw_n signal is
asserted, and the content of the temporary register is placed on the data bus. The
state machine samples the ready signal and stays in this state as long as it is
asserted. Then the machine transitions to state S24.
Input Signals: eopin_n , ready
Output Signals: memw_n
Possible State Transitions: S23, S24
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DMA-MC-SC-N3 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DMA-MC-XM-N3 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DMA-MC-XP-N2 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DM-A-PP | 制造商:DDK 制造商全称:DDK Ltd. 功能描述:Conversion Connector |
| DMA-SG-E3-U1 | 功能描述:开发软件 DMA Scatter/Gather RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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