- 您现在的位置：买卖IC网 > PDF目录16128 > DMA-MC-O4-N2 (Lattice Semiconductor Corporation)IP CORE MCDMA CTLR ORCA 4 PDF资料下载
参数资料
| 型号： | DMA-MC-O4-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IP CORE MCDMA CTLR ORCA 4 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | DMAMCO4N2 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
? Illegal I/O to memory transfer mode bits
? Compressed timing mode
FSM Operation
When a software or hardware request is received and is found to be valid (having passed the polarity, mask and
mode checks), the DMA FSM in SI (Idle) state transmits a request signal, hreq to the CPU and transitions to S0
and waits for the hlda signal. If the request drops ( dreq is de-asserted) or the mode register of the request in
hand is in cascade mode (unsupported), the FSM returns to SI (idle). Otherwise, the FSM remains in S0. Once the
request is acknowledged by the assertion of hlda signal, the FSM transitions to S1/S11 (S1 and S11 are synony-
mous).
The FSM also determines the transfer type based on the Command and Mode register that is received from the
CPU interface. If memory-to-memory transfer is enabled, the FSM transitions through states S12, S13, S14, S21,
S22, S23 and S24.
If the next transfer should continue for the same request, the path from S11 to S24 is repeated. If memory-to-I/O or
I/O-to-memory is enabled, the FSM goes through states S2, S3 (eliminated in 8237’s compressed timing mode),
and S4. If the transfer continues, the state machine repeats the loop from S2 through S4. This goes on until the
Word Count register gets an over?ow or a termination from an external input occurs. External inputs that can termi-
nate a transfer includes an eopin_n or hlda drop or a request drop during demand transfer. (Note: In case of a
non-demand transfer, the request can be dropped after dack is received.). The eopout_n signal is generated on
the falling clock edge of S4 or S24 by the end of the transfer. All transfer read/write signals are generated on the
falling edge of clock.
In the state machine described in Figure 2, “input signals” refer to the signals that the state machine samples.
These signals affect the state machine’s transition logic. “Output signals” refer to signals that will be asserted or de-
asserted (transition) while in that state.
5
相关PDF资料 |
PDF描述 |
|---|---|
| LHL10TB220K | INDUCTOR 22UH 2.1A RADIAL |
| EBC31DRTH | CONN EDGECARD 62POS DIP .100 SLD |
| LHL10TB183J | INDUCTOR 18000UH 81MA RADIAL |
| LHL10TB182J | INDUCTOR 1800UH .29A RADIAL |
| 1487EK | WIREWAY BOX CONNECTOR 8X8" |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DMA-MC-SC-N3 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DMA-MC-XM-N3 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DMA-MC-XP-N2 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DM-A-PP | 制造商:DDK 制造商全称:DDK Ltd. 功能描述:Conversion Connector |
| DMA-SG-E3-U1 | 功能描述:开发软件 DMA Scatter/Gather RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
发布紧急采购，3分钟左右您将得到回复。