参数资料
型号: DMA-MC-XP-N2
厂商: Lattice Semiconductor Corporation
文件页数: 16/28页
文件大小: 0K
描述: IP CORE MCDMA CTLR XPGA ISPXPGA
标准包装: 1
系列: *
其它名称: DMAMCXPN2
Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
Figure 5 shows the timing waveform for two words DMA transfer.
Figure 5. Two Word DMA Transfer Timing Waveform
Si
S0
S0
S1
S2
S3
S4
S2
S3
S4
Si
Clock
dreq
hreq
hlda
aen
aout
Valid Address
Valid Address
dack
iorout_n/memr_n
iowout_n/memw_n
Note 1.
Note 1. This timing diagram demonstrates the extended write operation. In the 8237 mode, when normal write operation is
selected, iowout_n or the memw_n is asserted one clock cycle later.
If compressed timing is selected, the state S3 is bypassed, making the read and write pulses of equal width. This is only
applicable in 8237 mode.
The iowout_n and memw_n signals are generated off the falling clock edge. This ensures the address is held at least for
half a cycle after the rising edge of the write signal.
16
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