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| 型号： | DMA-MC-XP-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IP CORE MCDMA CTLR XPGA ISPXPGA |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | DMAMCXPN2 |
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Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
Register Descriptions
The 8237 and non-8237 modes of the MCDMA Controller have different types and number of internal registers.
The 8237 mode has ten types of internal registers that are visible to the microprocessor while the non-8237 mode
has seven types of internal registers that are visible to the microprocessor.
8237 Mode Internal Registers
Table 5. Internal Registers in 8237 Mode
Name
Base Address Registers
Base Word Count Registers
Current Address Registers
Current Word Count Registers
Command Register
Status Register
Temporary Register
Mode Register
Mask register
Request Register
Size in Bits
16
16
16
16
8
8
8
8
8
4
Number of Registers
4
4
4
4
1
1
1
4
1
1
Current Address Register
This register is only available in the 8237 mode. Each of the four channels has a 16 -bit wide Current Address Reg-
ister that holds the value of the address used during DMA transfers. The address is automatically incremented or
decremented after each transfer. The microprocessor loads the Current Address Register simultaneously with the
Base Address Register. If Auto-Initialization is enabled, the MCDMA reloads the base address value at the end of
the DMA cycle. This register has to be written in two consecutive cycles after clearing the byte pointer.
Current Word Count Register
This register is only available in the 8237 mode. Each channel has a 16-bit Current Word Count register that deter-
mines the number of transfers to be performed. The actual number of transfers is one more than the value pro-
grammed into this register. The Current Word Count is decremented after each transfer. If Auto-Initialization is
enabled, the value in the Base Word Count register is reloaded at the end of the DMA service. When the value in
the register goes from zero to 0xFFFF, a terminal count ( eopout_n ) signal is generated. If Auto-Initialization is not
enabled, this register has a count of 0xFFFF at the end of DMA service.
Base Address Register
This register is only available in the 8237 mode. Each channel has a 16-bit Base Address Register. This register
stores the starting address for the transfer. In the idle state or program condition, the microprocessor simulta-
neously writes to the Base Address register and to the Current Address register. The microprocessor cannot read
this register.
Base Word Count Register
This register is available only in the 8237 mode. Each channel has a 16-bit Base Word Count register that stores
the starting word count for DMA transfers. During Auto-Initialization, this value is used to restore the current word
count register. The microprocessor cannot read this register.
Command Register
This register controls the operation of the core. In the 8237 mode, this register is 8 bits wide. In non-8237 mode, it
is 4 bits wide. When DMA is in state idle, the microprocessor programs this register. A reset or master clear clears
the register. Table 6 lists the function of this register.
17
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| DMA-SG-P2-UT1 | 功能描述:开发软件 DMA SCATTER/GATHER RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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