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参数资料
| 型号： | DMA-MC-XP-N2 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 2/28页 |
| 文件大小： | 0K |
| 描述： | IP CORE MCDMA CTLR XPGA ISPXPGA |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | DMAMCXPN2 |
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Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
Introduction
The Multi-Channel Direct Memory Access (MCDMA) Controller is designed to improve microprocessor system per-
formance by allowing external devices to transfer information directly from the system memory and vice versa.
Memory-to-memory transfer capability is also supported.
The MCDMA Controller core supports two modes of operation: 8237 and non-8237 modes. When the 8237 mode
is selected, the core is functionally compatible with the Intel 8237A DMA Controller device with a few variations.
These variations are listed in the Compatibility Differences with the 8237 Intel Device section of this document. The
8237 and non-8237 modes are detailed later in this document to provide a clearer description of each mode.
Differences Between 8237 Mode and Non-8237 Mode MCDMA
While the 8237 and non-8237 modes share some commonality, they also have differences. Table 1 shows the dif-
ferences between the two modes.
Table 1. Feature Differences Between the 8237 and Non-8237 Modes
Feature
Multiple independent channels
Parameterized address bus
Parameterized data bus
Parameterized word count register
Auto-initialization
Compressed timing
Cascade mode
DMA transfer con?guration for each channel
Priority request mode
DMA request active state
Software reset
8237 Mode
4
Fixed 16 bits
Fixed 8 bits
Fixed 16 bits
Supported
Supported
Not supported
Not supported
Rotating/?xed priority mode
High/low
Supported
Non-8237 Mode
1-16
16, 24 or 32 bits
8, 16, 32 or 64 bits
8, 16, 24 or 32 bits
Supported
Not supported
Not supported
Supported
Fixed priority mode
High
Not supported
Compatibility Differences with the 8237 Intel Device
When the MCDMA core is con?gured for the 8237 mode, it differs from the Intel 8237A core in the following ways:
? The bi-directional ports are split into separate input and output ports.
? MCDMA does not support the cascade mode of operation.
? The latch that holds the upper byte of the address is internal and the address strobe signal ADSTB is not gener-
ated.
The slave’s write cycle in the MCDMA core is synchronous.
Features
? Selectable 8237 mode
? Con?gurable up to 16 independent DMA channels for non-8237 mode
? Con?gurable data width of 8-, 16-, 32- or 64-bits for non-8237 mode
? Con?gurable address width of 16-, 24- or 32-bits for non-8237 mode
? Con?gurable Word Count register width for non-8237 mode
? Independent auto-initialization of all channels
? Memory-to-memory transfers on single, block, and demand transfer mode
? Memory block initialization
2
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| DM-A-PP | 制造商:DDK 制造商全称:DDK Ltd. 功能描述:Conversion Connector |
| DMA-SG-E3-U1 | 功能描述:开发软件 DMA Scatter/Gather RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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| DMA-SG-P2-U1 | 功能描述:开发软件 DMA Scatter/Gather RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| DMA-SG-P2-UT1 | 功能描述:开发软件 DMA SCATTER/GATHER RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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