参数资料
| 型号： | DO-CPLD-DK-J-G |
| 厂商： | Xilinx Inc |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER CPLD JAPANESE |
| 标准包装： | 1 |
| 系列： | CoolRunner™- II |
| 类型： | CPLD 开发套件 |
| 适用于相关产品： | CoolRunner-ll，XC9500XL |
| 所含物品： | 原型板，下载缆线，软件和文档 |
R
Terminations
Programming (ISP) mode, the bus-hold is not active. If the device loses V CCINT , the I/Os
are in a pull-up state. The Bus-hold is enabled by Vccint, but pulls to Vccio.
Impedance of the Bus-hold, Keeper, or Pull-up
The values given in this section are typical numbers that cannot be guaranteed as the
impedance varies over process, voltage, and temperature.
CoolRunner-II
The effective resistance of the termination circuitry varies with V CCIO .
At V CCIO = 1.8V, the effective resistance is typically 100 k Ω .
As V CCIO increases, the effective resistance decreases. Typical for V CCIO =3.3V is 42 k Ω .
The minimum resistance value presented by the termination circuitry is 20 k Ω .
CoolRunner XPLA3
The CoolRunner does not have a bus-hold. It does have an internal pull-up that has been
characterized at approximately 60 to 150 k Ω .
XC9500, XC9500XL, and XC9500XV
The bus hold impedance is approximately 25 k Ω , with a range of 15 k Ω to 70 k Ω (the lower
range at lower temperatures).
Half Latch
CoolRunner XPLA3
The CoolRunner XPLA3 has a half latch feature on the I/Os. The half latch is essentially a
pull-up that turns on only when the I/O pin voltage is in the linear region (not a 0, not a 1).
So, when the voltage at the pin is in the trip-point region or higher, the half latch is enabled.
The idea is that it prevents signals from floating, and therefore, saves power. This half latch
cannot be disabled.
The device data sheet states the following: “The I/O is configured as an input (or 3-stated
output), a half latch feature exists. This half latch pulls the input high (through a weak
pull-up) if the input should float and cross the threshold.”
This means that the half latch feature exists even when the pull-up is not selected. If you
want to pull down the input, a resistor strong enough to overcome the half latch must be
used. Xilinx recommends that any pull-down resistor value be 10 k Ω or less. Xilinx does
not recommend using CoolRunner XPLA3 devices in any design that requires I/O pins to
truly float.
Some CoolRunner XPLA3 devices appear to have a pull-up on the I/O pins when there is
no pull-up specified, this is due to the CoolRunner XPLA3 half latch circuitry. The range of
the trip-point is from 0.9V to 1.6V. There was a change in the trip-point when Xilinx
changed fabs. The change in fab locations is documented in PCNs, and is available on the
Xilinx Customer Notices page:
The trip-point for the newer devices (part marking of *MN) is lower than the trip-point for
the older devices (part marking of APN); this can result in the half latch circuitry being
“turned on” sooner than in the older devices. If this occurs, a pull-down resistor of a value
stronger than 10 k Ω is required to overcome the half latch pull-up resistance; a value of
CPLD I/O User Guide
UG445 (v1.2) January 14, 2014
11
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