参数资料
型号: DO-CPLD-DK-J-G
厂商: Xilinx Inc
文件页数: 19/24页
文件大小: 0K
描述: KIT STARTER CPLD JAPANESE
标准包装: 1
系列: CoolRunner™- II
类型: CPLD 开发套件
适用于相关产品: CoolRunner-ll,XC9500XL
所含物品: 原型板,下载缆线,软件和文档
R
Figure 5:
Power, Sequencing, and Slew Rates
UG445_04_052207
V CCINT is powered before V CCIO
For best results (with multiple power rails), Xilinx recommends that V CCINT be applied
before V CCIO (see Figure 5 ); this ensures that the internal logic is correct before the I/Os are
active. If V CCIO is powered before V CCINT , this does not damage the device, but there
might be glitches on the I/O as the internal circuitry is initialized. Xilinx recommends not
leaving V CCIO floating while V CCINT is ramping.
During power-up, all Xilinx CPLDs employ internal circuitry which keeps the devices in
the quiescent state (weak pull-up) until the V CCINT supply voltage is at a safe level.
The approximate “safe level” for each device is listed below:
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CoolRunner-II: 1.3V
CoolRunner XPLA3: 2.1V
XC9500XL: 2.5V
XC9500XV: 1.9V
XC9500: 3.8V
V CCIO can be removed without damaging the part, but the exact behavior under these
conditions is not characterized, and therefore, not recommended. When power is removed
from V CCIO with the core powered, the I/Os still try to drive and read their pins.
Transistors are in an unknown state, which results in more current than if the I/Os were
disabled or held in a known state.
V CCIO is not required for programming of the non-volatile memory of a CoolRunner-II.
However, it is strongly recommended to power V CCIO during programming. For the
XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 devices, V CCIO is required for
configuration and programming.
V CCAUX is used to power the JTAG circuitry. This leads to a common question, can V CCAUX
be safely removed after configuration. This is not recommend. V CCAUX should be powered
even after configuration. If there are no JTAG instructions, the power consumed on
CPLD I/O User Guide
UG445 (v1.2) January 14, 2014
19
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