参数资料
| 型号： | DO-CPLD-DK-J-G |
| 厂商： | Xilinx Inc |
| 文件页数： | 22/24页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER CPLD JAPANESE |
| 标准包装： | 1 |
| 系列： | CoolRunner™- II |
| 类型： | CPLD 开发套件 |
| 适用于相关产品： | CoolRunner-ll，XC9500XL |
| 所含物品： | 原型板，下载缆线，软件和文档 |
Power, Sequencing, and Slew Rates
The following is sample code for how to achieve the fast rise in VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port ( data : in std_logic; data_to_pin : inout std_logic);
end top;
architecture Behavioral of top is
begin
data_to_pin<= data when ((data and data_to_pin) ='0') else 'Z';
end Behavioral;
Code for Verilog:
module top(data, data_to_pin );
input data;
inout data_to_pin ;
assign data_to_pin = ((data & data_to_pin) == 0)? data : 1'bz;
endmodule
I/O Standards
The supported I/O standards for the different CPLD families are as follows:
R
?
?
?
XC9500, XC9500XL, and XC9500XV: LVTTL, LVCMOS33
CoolRunner XPLA3: LVCMOS33
CoolRunner-II: LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, HSTL_1,
SSTL2_1, SSTL3_1, and LVCMOS15 require use of Schmitt trigger inputs.
Simultaneous Switching Output Limits
Xilinx does not characterize the CPLD device packages to estimate the maximum number
of Simultaneous Switching Outputs (SSOs) before ground bounce. However, Xilinx
recommends that you not have more than 8 SSOs on the entire chip (all banks included).
If you need to have more than 8 SSOs, Xilinx recommends that you consider altering the
slew rate setting on these outputs to skew the outputs relative to each other. By following
this recommendation, you can avoid ground bounce due to SSOs.
Decoupling Guidelines
The minimum decoupling recommendations for CPLD devices are to provide both 0.1 and
0.01 uF capacitors at every V CC point of the chip and attach them directly to the nearest
ground.
Schmitt Trigger
CoolRunner-II is the only family to have the Schmitt trigger feature. A Schmitt trigger is an
input circuit used to reduce noise on the input signal. In CoolRunner-II devices, there is a
Schmitt trigger available on all I/Os, but only with the I/O standards that do not require a
VREF.
22
CPLD I/O User Guide
UG445 (v1.2) January 14, 2014
相关PDF资料 |
PDF描述 |
|---|---|
| DP-4XL | EPOXY ADHESIVE DUO-PACK 37ML |
| DP1R020JQ3 | CONN RCPT 20POS RT ANG TOP MNT |
| DP1RD20JQ1R400 | CONN RCPT 20POS R/A TOP MT GOLD |
| DP1RD20JQ1 | CONN RCPT 20POS R/A TOP MT GOLD |
| DP270 EPOXY BLACK | POTTING COMPOUND BLACK GAL KIT |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DO-CSP-PRO-52 | 制造商:Xilinx 功能描述:TIME BASED LICENSE DEVT OPT EOL260308 |
| DO-CSP-PRO-USB-G | 功能描述:KIT CHIPSCOPE PRO W/USB II RoHS:是 类别:测试设备 >> 示波器 系列:ChipScope™ Pro 标准包装:1 系列:2542 类型:工作台 - 数字 带宽:100MHz 通道:2 显示器类型:LCD - 彩色 接口:LAN，RS232，USB 存储容量:16kpts 功能:记录、回放、保存、趋势 探头类型:无源 10:1（2） 采样率（每秒）:1G 输入阻抗:1M - 18pF 上升时间（标准值）:3.5ns 电压 - 输入（最大）:CAT I 400V 电源电压:100 ~ 240VAC 包括:电线，手册，探头，USB 电缆 其它名称:BK2542B |
| DO-CSP-PRO-USB-II-G-FL | 功能描述:CHIPSCOPE PRO WITH USB-II CABLE RoHS:是 类别:编程器，开发系统 >> 软件 系列:ChipScope™ Pro 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| DO-CSP-PRO-USB-II-G-NL | 功能描述:CHIPSCOPE PRO WITH USB-II CABLE RoHS:是 类别:编程器，开发系统 >> 软件 系列:ChipScope™ Pro 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| DOC-ST7-EMU3/DS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ST7-EMU3 EMULATOR FOR ST7XXXX DEVICES |
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