参数资料
| 型号： | DO-CPLD-DK-J-G |
| 厂商： | Xilinx Inc |
| 文件页数： | 12/24页 |
| 文件大小： | 0K |
| 描述： | KIT STARTER CPLD JAPANESE |
| 标准包装： | 1 |
| 系列： | CoolRunner™- II |
| 类型： | CPLD 开发套件 |
| 适用于相关产品： | CoolRunner-ll，XC9500XL |
| 所含物品： | 原型板，下载缆线，软件和文档 |
Thresholds
R
4.7 k Ω is recommended. If the incorrect value of a pull-down is used, a voltage divider is
created at the input.
More information on the half latch is available in the XPLA3 I/O Cell Characteristics
Application Note ( XAPP342 ).
CoolRunner-II
The CoolRunner-II I/Os have a half latch feature enabled by default. Half latch occurs only
in cases when the CoolRunner-II I/Os are configured as LVCMOS18 and the Schmitt
trigger is disabled. If the Schmitt trigger is used, the half latch is disabled. When using
LVCMOS18, the only way to turn the half latch off is to enable the Schmitt trigger on that
input.
XC9500, XC9500XL, and XC9500XV
The XC9500 families do not have a half latch.
The XC9500XL and XC9500XV have internal circuitries that function in a similar manner to
a half latch. To overcome this circuitry, ensure that a pull-down of 4.7 k Ω or stronger is
used. (The effective resistance of the internal circuitry is between 30 to 60 k Ω .)
JTAG Termination
XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 have internal pull-ups on TDI
and TMS.
CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK.
It is recommended to place external pull-up resistors on the JTAG input pins TDI, TMS,
and TCK. For a single device, the resistor value of 4.7 k Ω is suggested. This value may be
adjusted depending on the number of devices in the JTAG chain or the application.
External pull-down termination is not recommended as it would conflict with the internal
pull-ups.
Thresholds
I/V Curves
The I/V curve is a graphical representation of the nominal amount of current that an I/O
can source or sink at different voltage levels. The range of voltage levels, and therefore, the
current, is dependent on the I/O voltage used. The I/V curves provide details on
thresholds.
The I/V curves for the CoolRunner-II and CoolRunner XPLA3 devices can be found in the
family data sheets and in the I/V Curves for Xilinx FPGA and CPLD Families Application Note
Questions often asked by users are:
?
?
How much current can an I/O source or sink?
If I am driving a certain load, what voltage levels can I expect?
12
CPLD I/O User Guide
UG445 (v1.2) January 14, 2014
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DO-CSP-PRO-52 | 制造商:Xilinx 功能描述:TIME BASED LICENSE DEVT OPT EOL260308 |
| DO-CSP-PRO-USB-G | 功能描述:KIT CHIPSCOPE PRO W/USB II RoHS:是 类别:测试设备 >> 示波器 系列:ChipScope™ Pro 标准包装:1 系列:2542 类型:工作台 - 数字 带宽:100MHz 通道:2 显示器类型:LCD - 彩色 接口:LAN，RS232，USB 存储容量:16kpts 功能:记录、回放、保存、趋势 探头类型:无源 10:1（2） 采样率（每秒）:1G 输入阻抗:1M - 18pF 上升时间（标准值）:3.5ns 电压 - 输入（最大）:CAT I 400V 电源电压:100 ~ 240VAC 包括:电线，手册，探头，USB 电缆 其它名称:BK2542B |
| DO-CSP-PRO-USB-II-G-FL | 功能描述:CHIPSCOPE PRO WITH USB-II CABLE RoHS:是 类别:编程器，开发系统 >> 软件 系列:ChipScope™ Pro 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| DO-CSP-PRO-USB-II-G-NL | 功能描述:CHIPSCOPE PRO WITH USB-II CABLE RoHS:是 类别:编程器，开发系统 >> 软件 系列:ChipScope™ Pro 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384 |
| DOC-ST7-EMU3/DS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ST7-EMU3 EMULATOR FOR ST7XXXX DEVICES |
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