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参数资料
| 型号： | DP5Z2MW16PH3-15C |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 5V PROM MODULE, 120 ns, QFP48 |
| 封装： | HERMETIC SEALED, CERAMIC, GULLWING, MODULE, SLCC-48 |
| 文件页数： | 19/21页 |
| 文件大小： | 4549K |
| 代理商： | DP5Z2MW16PH3-15C |
Dense-Pac Microsystems, Inc.
DP5Z2MW16Pn3
PRELIMINARY
registers are not reset during sleep command. Program or Erase
fail bit may have been set if during program/erase mode the device
retry exceeds maximum count.
During Sleep mode, the status registers, Silicon ID codes remain
valid and can still be read. The device Sleep Status bit - I/O2 will
indicate that the device in the sleep mode.
Write and Read Array command wakes up the device out of Sleep
mode, I/O2 is reset to “0" and device returns to standby current
level.
ABORT MODE
To activate Abort mode, a three-bus cycle operation is required.
The E0H command (refer to Table 3) only stops page program or
Sector/Chip erase operations currently in progress and puts the
device in Sleep mode. But unlike the Sleep command, the
program or erase operation will not be completed. Since the data
in some page/sectors is no longer valid due to an incomplete
program or erase operation, the program fail (I/O4) or erase fail
(I/O5) bit will be set.
After the abort command is executed and with CMOS input levels
applied, the device current is reduced to the same level as in deep
power-down or sleep modes. Device stays at read register mode.
During Abort mode, the status register, Silicon ID codes remain
valid and can still be read. The device Sleep Status bit - I/O2 will
indicate that the device in the sleep mode.
DATA PROTECTION
The device is designed to offer protection against accidental
erasure or programming caused by spurious system level signals
that may exit during power transitions. During power-up the
device automatically resets the internal state machine in the read
array mode. Also, with its control register architecture, alterations
of the memory contents only occurs after successful completion of
specific multi-bus cycles command sequences.
the device also incorporates several features to prevent inadvertent
write cycles resulting from VDD power-up and power-down
transitions or system noise.
LOW VDD WRITE INHIBIT
To avoid initiation of a write cycle during VDD power-up and
power-down, a write cycle is locked out for VDD less than VOKL
(=3.2V, typically 3.5V). If VDD < VLKO, the command register is
disabled and all internal program/erase circuits are disabled.
Under this condition the device will reset to the read mode.
Subsequent writes will be ignored until the VDD level is greater
than VLKO. It is logically correct to prevent unintentional write
when VDD is above VLKO.
WRITE PULSE “GLITCH” PROTECTION
Noise pulses of less than 10ns (typical) on CE or WE will not initiate
a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE = VIH or
WE = VIH. To initiate a write cycle CE and WE must be a logical
zero while OE is a logical one.
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
LIMITS
UNITS
MIN.
TYP.
MAX.
Chip/Sector Erase Time
150
2000
ms
Page Programming Time
3
60
ms
Chip Program Time
48
150
sec
Erase/Program Cycles
10,000
Cycles
Byte Program Time
24
s
LATCH UP CHARACTERISTICS
PARAMETER
MIN.
AMX.
UNITS
Input Voltage with Respect to VSS on all pins except I/O pins
-1.0
13.5
V
Input Voltage with Respect to VSS on all I/O pins
-1.0
VDD +1.0
V
Current
-100
+100
mA
Includes all pins except VDD. Test conditions: VDD = 5.0V, one pin at a time
30A161-22
REV. B
7
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