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参数资料
| 型号： | DP5Z2MW16PH3-15C |
| 元件分类： | PROM |
| 英文描述： | 2M X 16 FLASH 5V PROM MODULE, 120 ns, QFP48 |
| 封装： | HERMETIC SEALED, CERAMIC, GULLWING, MODULE, SLCC-48 |
| 文件页数： | 6/21页 |
| 文件大小： | 4549K |
| 代理商： | DP5Z2MW16PH3-15C |
DP5Z2MW16Pn3
Dense-Pac Microsystems, Inc.
PRELIMINARY
Figure 5: READ CYCLE
ADDRESS
CE
OE
WE
DATA I/O
VDD
AC Operating Conditions and Characteristics - Write/Erase/Program Cycle: Over operating ranges
No. Symbol
Parameter
120ns
150ns
200ns
Unit
Min.
Max.
Min.
Max.
Min.
Max.
6
tWC
Write Cycle Time
120
150
200
ns
7
tAS
Address Setup Time
0
ns
8
tAH
Address Hold Time
50
60
70
ns
9
tDS
Data Setup Time
50
60
70
ns
10
tDH
Data Hold Time
10
ns
11
tOES
Output Enable Setup Time
0
ns
12
tCES
Chip Enable Setup Time
0
ns
13
tGHWL
Read Recovery Time before Write
0
ns
14
tCS
Chip Enable Setup Time
0
ns
15
tCH
Chip Enable Hold Hold Time
0
ns
16
tWP
Write Pulse Width
50
60
70
ns
17
tWPH
Write Pulse Width HIGH
50
ns
18
tBALC
Byte Address Load Cycle
0.3
30
0.3
30
0.3
30
s
19
tBAL
Byte Address Load Time
100
s
20
tSRA
Status Register Access Time
120
150
200
ns
21
tCESR
Chip Enable Setup before SR Read
100
ns
22
tVCS
VDD Setup Time
2
s
30A161-22
REV. B
14
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