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参数资料
| 型号： | DS1250AB |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | DRAM |
| 英文描述： | 4096K Nonvolatile SRAM(4096K 非易失性静态RAM) |
| 中文描述： | 512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA32 |
| 文件页数： | 7/11页 |
| 文件大小： | 111K |
| 代理商： | DS1250AB |
DS1250Y/AB
042398 7/11
POWER–DOWN/POWER–UP TIMING
(t
A
: See Note 10)
UNITS
PARAMETER
SYMBOL
MIN
TYP
MAX
NOTES
CE, WE at V
IH
before
Power–Down
t
PD
0
μ
s
11
V
CC
Slew from V
TP
to 0V
t
F
300
μ
s
V
CC
Slew from 0V to V
TP
t
R
300
μ
s
CE, WE at V
IH
after Power–Up
t
REC
2
125
ms
(t
A
= 25
°
C)
NOTES
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Expected Data Retention Time
t
DR
10
years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = V
IH
or V
IL
. If OE = V
IH
during write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of CE and WE. t
WP
is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. t
DH
, t
DS
are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain
in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
remain in a high impedance state during this period.
9. Each DS1250 has a built–in switch that disconnects the lithium source until V
CC
is first applied by the user. The
expected t
DR
is defined as accumulative time in the absence of V
CC
starting from the time power is first applied
by the user.
10.All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial prod-
ucts, this range is 0
°
C to 70
°
C. For industrial products (IND), this range is –40
°
C to +85
°
C.
11. In a power–down condition the voltage on any pin may not exceed the voltage on V
CC
.
12.t
WR1
and t
DH1
are measured from WE going high.
13.t
WR2
and t
DH2
are measured from CE going high.
14.DS1250 DIP modules are recognized by Underwriters Laboratory (U.L.
) under file E99151. DS1250 PowerCap
modules are pending U.L. review. Contact the factory for status.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1250Y | 4096K Nonvolatile SRAM(4096K 非易失性静态RAM) |
| DS1250W | 3.3V 4096K Nonvolatile SRAM(3.3V 4096K 非易失性静态RAM) |
| DS1251Y | 4096K NV SRAM with Phantom Clock(带幻影时钟的4096K NV 静态RAM) |
| DS1258AB | 128K x 16 Nonvolatile SRAM(128K x 16 非易失性静态RAM) |
| DS1258Y | 128K x 16 Nonvolatile SRAM(128K x 16 非易失性静态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1250AB-100 | 功能描述:NVRAM 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250AB-100+ | 功能描述:NVRAM 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250AB-100IND | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1250AB-100-IND | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
| DS1250AB-100IND+ | 功能描述:NVRAM 4096K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
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