- 您现在的位置：买卖IC网 > PDF目录4573 > DS1865T+T&R (Maxim Integrated Products)IC PON CONTROL TRI 28-TQFN PDF资料下载
参数资料
| 型号： | DS1865T+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/67页 |
| 文件大小： | 0K |
| 描述： | IC PON CONTROL TRI 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | * |
| 类型： | * |
| 应用： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页
DS1865
PON Triplexer Control and
Monitoring Circuit
____________________________________________________________________
19
I2C Definitions
The following terminology is commonly used to
describe I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data at
the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle, it often initi-
ates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 9 for
applicable timing.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 9 for
applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated START
conditions are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 9 for
applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (Figure 9). Data is shift-
ed into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock puls-
es including when it is reading bits from the slave.
Acknowledgement (ACK and NACK): An acknowledge-
ment (ACK) or not acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmit-
ting a zero during the 9th bit. A device performs a
NACK by transmitting a one during the 9th bit. Timing
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave addressing byte (Figure 9) sent
immediately following a START condition. The slave
address byte contains the slave address in the most sig-
nificant 7 bits and the R/W bit in the least significant bit.
The DS1865 responds to two slave addresses. The auxil-
iary memory always responds to a fixed I2C slave address,
A0h. The Lower Memory and tables 01h–06h respond to
I2C slave addresses that can be configured to any value
between 00h–FEh using the Device Address byte (Table
02h, Register 8Ch). The user also must set the ASEL bit
(Table 02h, Register 89h) for this address to be active. By
writing the correct slave address with R/W = 0, the master
indicates it will write data to the slave. If R/W = 1, the mas-
ter reads data from the slave. If an incorrect slave address
is written, the DS1865 assumes the master is communicat-
ing with another I2C device and ignores the communica-
tions until the next START condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
相关PDF资料 |
PDF描述 |
|---|---|
| TLE8264E | IC SYSTEM BASIS CHIP DSO-36 |
| MAX4507CWN+T | IC SIGNAL LINE PROTECTOR 18-SOIC |
| TLE8263-2E | IC SYSTEM BASIS CHIP DSO-36 |
| TLE8263E | IC SYSTEM BASIS CHIP DSO-36 |
| TLE8262E | IC SYSTEM BASIS CHIP DSO-36 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1866 | 功能描述:数字电位计 IC RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
| DS1866+ | 功能描述:数字电位计 IC Log Trimmer RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
| DS1866N | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Interface IC |
| DS1866S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Interface IC |
| DS1866SN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Interface IC |
发布紧急采购，3分钟左右您将得到回复。