参数资料
型号: DS1865T+T&R
厂商: Maxim Integrated Products
文件页数: 4/67页
文件大小: 0K
描述: IC PON CONTROL TRI 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: *
类型: *
应用: *
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
DS1865
PON Triplexer Control and
Monitoring Circuit
12
____________________________________________________________________
bias update comparison was above the APC set point,
and checks LTXP to see if the last bias update compari-
son was below the APC set point. Depending on the
results of the comparison, the corresponding alarms
and warnings (TXP-HI, TXP-LO) are asserted or
deasserted.
The DS1865 has a programmable comparator sample
time based on an internally generated clock to facilitate a
wide variety of external filtering options suitable
for burst-mode transmitter data rates between 155Mbps
and 1250Mbps. The rising edge of the burst enable
(BEN) triggers the sample to occur, and the Update Rate
register (Table 02h, Register 88h) determines the sam-
pling time. The first sample occurs tFIRST after the rising
edge of BEN. The internal clock is asynchronous to BEN,
causing a ±50ns uncertainty regarding when the first
sample will occur following BEN. After the first sample
occurs, subsequent samples occur on a regular interval,
tREP. Table 2 shows the sample rate options available.
1
2
3
4
5
6
7
8
9
10
11
12
13
tINIT
VPOA
BINARY SEARCH
APC
INTEGRATOR
ON
tSEARCH
VMOD
IBIAS
VCC
BIAS
SAMPLE
ISTEP
4x ISTEP
3x ISTEP
2x ISTEP
Figure 1. Power-Up Timing
TX-D
IBIAS
VMOD
tOFF
tON
tOFF
Figure 2. TX-D Timing (Normal Operating Conditions)
Table 2. Update Rate Timing
SR3–SR0
MINIMUM TIME
FROM BEN TO
FIRST SAMPLE
(tFIRST) ±50ns
REPEATED
SAMPLE PERIOD
FOLLOWING FIRST
SAMPLE (tREP)
0000b
350ns
800ns
0001b
550ns
1200ns
0010b
750ns
1600ns
0011b
950ns
2000ns
0100b
1350ns
2800ns
0101b
1550ns
3200ns
0110b
1750ns
3600ns
0111b
2150ns
4400ns
1000b
2950ns
6000ns
1001b*
3150ns
6400ns
*
All codes greater than 1001b (1010b–1111b) use the maximum
sample time of code 1001b.
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