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| 型号： | DS1865T+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/67页 |
| 文件大小： | 0K |
| 描述： | IC PON CONTROL TRI 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | * |
| 类型： | * |
| 应用： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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DS1865
PON Triplexer Control and
Monitoring Circuit
____________________________________________________________________
17
Digital I/O Pins
Five digital I/O pins are provided for additional monitor-
ing and control of the triplexer. By default the LOSI pin
is used to convert a standard comparator output for
loss of signal (LOSI) to an open-collector output. This
means the mux shown on the block diagram by default
selects the LOSI pin as the source for the D0 output
transistor. The level of the D0 pin can be read in the
status byte (Lower Memory, Register 6Eh) as the LOS
status bit. The LOS status bit reports back the logic
level of the D0 pin, so an external pullup resistor must
be provided for this pin to output a high level. The LOSI
signal can be inverted before driving the open-drain
output transistor using the XOR gate provided. The
mux LOSI allows the D0 pin to be used identically to the
D1, D2, and D3 pins. However, the mux setting (stored
in the EEPROM) does not take effect until VCC > VPOA,
allowing the EEPROM to recall. This requires the LOSI
pin to be grounded for D0 to act identical to the D1, D2,
and D3 pins.
Digital pins D1, D2, and D3 can be used as inputs or
outputs. External pullup resistors must be provided to
realize high logic levels. The levels of these input pins
can be read by reading the DIN byte (Lower Memory,
Register 79h), and the open-drain outputs can be con-
trolled using the DOUT byte (Lower Memory, Register
78h). When VCC < VPOA, these outputs are high imped-
ance. Once VCC
≥ VPOA, the outputs go to the power-on
default state stored in the DPU byte (Table 02h, Register
C0h). The EEPROM determined default state of the pin
can be modified with PW2 access. After the default state
has been recalled, the SRAM registers controlling out-
puts can be modified without password access. This
allows the outputs to be used to control serial interfaces
without wearing out the default EEPROM setting.
Memory Organization
The DS1865 features eight banks of memory composed
of the following.
The Lower Memory is addressed from 00h to 7Fh
and contains alarm and warning thresholds, flags,
masks, several control registers, password entry
area (PWE), and the table select byte. The table
select byte determines which table (01h–06h) will be
mapped into the upper memory locations, namely
80h–FFh (unless stated otherwise).
Table 01h primarily contains user EEPROM (with
PW1 level access) as well as some alarm and warn-
ing status bytes.
Table 02h is a multifunction space that contains
configuration registers, scaling and offset values,
passwords, interrupt registers, as well as other mis-
cellaneous control bytes.
Table 03h is strictly user EEPROM that is protected
by a PW2 level access.
Table 04h contains a temperature-indexed LUT for
control of the modulation voltage. The modulation
LUT can be programmed in 2°C increments over the
-40°C to +102°C range. This register is protected by
a PW2 level access.
Table 05h contains another LUT, which allows the
APC set point to change as a function of tempera-
ture to compensate for tracking error (TE). This TE
LUT has 36 entries that determine the APC setting
in 4°C windows between -40°C to +100°C. This reg-
ister is protected by a PW2 level access.
VCC
VPOA
VPOD
FETG
SEE*
*SEE = SHADOWED EEPROM
HIGH
IMPEDANCE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
NORMAL
OPERATION
DRIVEN TO
FETG DIR
NORMAL
OPERATION
PRECHARGED
TO 0
PRECHARGED
TO 0
PRECHARGED
TO 0
RECALLED
VALUE
RECALLED
VALUE
DRIVEN TO
FETG DIR
NORMAL
OPERATION
DRIVEN TO
FETG DIR
SEE RECALL
Figure 7. Low-Voltage Hysteresis Example
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