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参数资料
| 型号： | DS1865T+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/67页 |
| 文件大小： | 0K |
| 描述： | IC PON CONTROL TRI 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | * |
| 类型： | * |
| 应用： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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DS1865
PON Triplexer Control and
Monitoring Circuit
16
____________________________________________________________________
the first SEE recall, but the device analog is shut down
and the outputs are disabled. FETG is driven to its
alarm state defined by the FETG DIR bit (Table 02h,
Register 89h). If the supply voltage recovers back
above VPOA, the device immediately resumes normal
functioning. If the supply voltage falls below VPOD, the
device SRAM is placed in its default state and another
SEE recall is required to reload the nonvolatile settings.
The EEPROM recall occurs the next time VCC exceeds
VPOA. Figure 7 shows the sequence of events as the
voltage varies.
Any time VCC is above VPOD, the I2C interface can be
used to determine if VCC is below the VPOA level. This is
accomplished by checking the RDYB bit in the status
(Lower Memory, Register 6Eh) byte. RDYB is set when
VCC is below VPOA. When VCC rises above VPOA, RDYB
is timed (within 500s) to go to 0, at which point the part
is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until VCC exceeds VPOA allowing the device address to
be recalled from the EEPROM.
Power-On Analog (POA)
POA holds the DS1865 in reset until VCC is at a suitable
level (VCC > VPOA) for the part to accurately measure
with its ADC and compare analog signals with its quick-
trip monitors. Because VCC cannot be measured by the
ADC when VCC is less than VPOA, POA also asserts the
VCC low alarm, which is cleared by a VCC ADC conver-
sion greater than the customer-programmable VCC low
ADC limit. This prevents the TX-F and FETG outputs
from glitching during a slow power-up. The TX-F and
FETG outputs do not latch until there is a conversion
above VCC low limit.
The POA alarm is nonmaskable. The TX-F and FETG
outputs are asserted when VCC is below VPOA. See the
Low-Voltage Operation section for more information.
DAC1 Output
The DAC1 output has a 0 to 2.5V range, 8 bits of resolu-
tion, and is programmed through the I2C interface. The
DAC1 setting is nonvolatile and password 2 (PW2) pro-
tected.
M4DAC Output
The M4DAC output has a 0 to 2.5V range, 8 bits of res-
olution, and is controlled by an LUT indexed by the
MON4 voltage. The M4DAC LUT (Table 06h) is non-
volatile and PW2 protected. See the
Memory
Organization section for details.
IBIAS
VMOD
DETECTION OF
FETG FAULT
tOFF
tON
tOFF
TX-D
tFETG:ON
FETG*
*FETG DIR = 0
tFETG:OFF
Figure 6. FETG/Modulation and Bias Timing (Fault Condition Detected)
Table 5. FETG, MOD, and BIAS Outputs
as a Function of TX-D and Alarm Sources
VCC >
VPOA
TX-D
NONMASKED
FETG ALARM
FETG
MOD AND
BIAS
OUTPUTS
Yes
0
FETG DIR
Enabled
Yes
0
1
FETG DIR
Disabled
Yes
1
X
FETG DIR
Disabled
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