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参数资料
| 型号： | DS1870E-010+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR RF POWER AMP 16TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1,000 |
| RF 型： | 手机 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
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LDMOS RF Power-Amplifier Bias
Controller
AC ELECTRICAL CHARACTERISTICS
(V CC = +4.5V to 5.5V, T A = -40°C to +95°C, timing referenced to V IL(MAX) and V IH(MIN) .) (Figure 3)
PARAMETER
SCL Clock Frequency
SYMBOL
f SCL
(Note 7)
CONDITIONS
MIN
0
TYP
MAX
400
UNITS
kHz
Bus Free Time Between Stop and
Start Conditions
Hold Time (Repeated) Start
Condition
Low Period of SCL
High Period of SCL
t BUF
t HD:STA
t LOW
t HIGH
1.3
0.6
1.3
0.6
μs
μs
μs
μs
Data Hold Time
Data Setup Time
Start Setup Time
t HD:DAT
t SU:DAT
t SU:STA
0
100
0.6
0.9
μs
ns
μs
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Setup Time
SDA and SCL Capacitive
Loading
EEPROM Write Time
t R
t F
t SU:STO
C B
t W
(Note 8)
(Note 8)
(Note 8)
(Note 9)
20 +
0.1C B
20 +
0.1C B
0.6
10
300
300
400
20
ns
ns
μs
pF
ms
NONVOLATILE MEMORY CHARACTERISTICS
(V CC = +4.5V to 5.5V, T A = 0°C to +70°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Writes
+70°C (Note 5)
50,000
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
All voltages referenced to ground.
Supply current is measured with all logic inputs at their inactive state (SDA = SCL = V CC ) and driven to well-defined logic
levels. All outputs are disconnected.
Absolute linearity is the difference of measured value from expected value at the DAC position. Expected value is a
straight line from measured minimum position to measured maximum position.
Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. Expected LSB change is
the slope of the straight line from measured minimum position to measured maximum position.
This parameter is guaranteed by design.
See Figure 1.
I 2 C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I 2 C stan-
dard-mode timing.
C B —total capacitance of one bus line in picofarads.
EEPROM write begins after a stop condition occurs.
_____________________________________________________________________
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