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| 型号： | DS1875T+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 20/92页 |
| 文件大小： | 0K |
| 描述： | IC SFP CTRLR/TRIPLEXER 38-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 应用： | 光纤 |
| 接口： | I²C |
| 电源电压： | 2.85 V ~ 3.9 V |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-TQFN（5x7） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 1431 (CN2011-ZH PDF) |
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DS1875
Stability and Compensation Component Selection
The components connected to the COMP pin (RCOMP
and CCOMP) introduce a pole and zero that are neces-
sary for stable operation of the PWM controller
(Figure 12).
The dominant pole, POLE1, is formed by the output
impedance of the error amplifier (REA) and CCOMP. The
zero formed by the components on COMP, ZERO1, is
selected to cancel POLE2 formed by the output filter
cap C3 and output load RLOAD. The additional pole,
POLE3, formed by R1 and C3 should be at least a
decade past the crossover frequency to not affect sta-
bility. The following formulas can be used to calculate
the poles and zero for the application shown in
Figure 12.
POLE1 (dominant pole) = 1/(2
π × REA × CCOMP)
ZERO1 (compensation zero) = 1/(2
π × RCOMP × CCOMP)
POLE2 (output load pole) =
POLE3 (output filter pole) = 1/(2
π × R1 × C3)
The DC open-loop gain is given by:
Where:
REA = 260MΩ
GM = 425S
RLOAD = Parallel combination of feedback network and
load resistance
VOUT = Output of DC-DC converter
VIN = DC-DC converter input voltage
VFB = Feedback voltage at the FB pin
T = Time period of switching frequency (seconds)
L = Inductor value (henries)
DAC1 Output
The DAC1 output has a full-scale 2.5V range with 8 bits
of resolution, and is programmed through the I2C inter-
face. The DAC1 setting is nonvolatile and password-2
(PW2) protected.
M4DAC Output
The M4DAC output has a full-scale 2.5V range with 8
bits of resolution, and is controlled by an LUT indexed
by the MON4 voltage. The M4DAC LUT (Table 06h) is
nonvolatile and PW2 protected. See the
Memory
Organization section for details. The recalled value is
either 16-bit or 32-bit depending on bits DBL_SB and
UP_LOWB in Table 02h, Register C7h.
Digital I/O Pins
Five digital I/O pins are provided for additional monitor-
ing and control. By default the LOSI pin is used to con-
vert a standard comparator output for loss of signal
(LOSI) to an open-collector output. This means the mux
shown on the block diagram by default selects the LOSI
pin as the source for the D0 output transistor. The level
of the D0 pin can be read in the STATUS byte (Lower
Memory, Register 6Eh) as the LOS STATUS bit. The
LOS STATUS bit reports back the logic level of the D0
pin, so an external pullup resistor must be provided for
this pin to output a high level. The LOSI signal can be
inverted before driving the open-drain output transistor
using the XOR gate provided. The MUX LOS allows the
D0 pin to be used identically to the D1, D2, and D3
pins. However, the mux setting (stored in the EEPROM)
does not take effect until VCC > VPOA, allowing the EEP-
ROM to recall. This requires the LOSI pin to be ground-
ed for D0 to act identical to the D1, D2, and D3 pins.
Digital pins D1, D2, and D3 can be used as inputs or
outputs. External pullup resistors must be provided to
realize high-logic levels. The DIN byte indicates the
logic levels of these input pins (Lower Memory, Register
79h), and the open-drain outputs can be controlled
using the DOUT byte (Lower Memory, Register 78h).
When VCC < VPOA, these outputs are high impedance.
Once VCC ≥ VPOA, the outputs go to the power-on
default state stored in the DPU byte (Table 02h, Register
C0h). The EEPROM-determined default state of the pin
can be modified with PW2 access. After the default
state has been recalled, the SRAM registers controlling
outputs can be modified without password access. This
allows the outputs to be used to control serial interfaces
without wearing out the default EEPROM setting.
D2 can be configured as the output of a quick-trip mon-
itor for MON3. The main application is to quickly shut
down the PWM converter and discharge the voltage
created by the converter. This is shown in the typical
application circuit.
AOL
G
R
VV
MEA
FB
IN
OUT
IN
OUT
IN
=×
×
085
2
.
V
RT
L
OUT
LOAD
×
2
1
22
3
×
×
××
+
()
VV
R
C
OUT
IN
OUT
IN
LOAD
π
PON Triplexer and SFP Controller
______________________________________________________________________________________
27
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1875T+ | 功能描述:ADC / DAC多通道 PON Triplexer & SFP Controller RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| DS1875T+T&R | 制造商:Maxim Integrated Products 功能描述:PON TRIPLEXER 38TQFN EP - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC SFP CTRLR/TRIPLEXER 38-TQFN 制造商:Maxim Integrated Products 功能描述:ADC / DAC Multichannel PON Triplexer & SFP Controller |
| DS1875T+T&R | 功能描述:ADC / DAC多通道 PON Triplexer & SFP Controller RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| DS1875T+TR | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:PON Triplexer and SFP Controller |
| DS1876 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:SFP Controller with Dual LDD Interface |
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