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参数资料
| 型号： | DS2045W-100# |
| 厂商： | Maxim Integrated |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 1MBIT 100NS 256BGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | NVSRAM（非易失 SRAM） |
| 存储容量： | 1M (128K x 8) |
| 速度： | 100ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（27x27） |
| 包装： | 托盘 |
DS2045W 3.3V Single-Piece 1Mb
Nonvolatile SRAM
Memory Operation Truth Table
WE
1
1
0
X
CE
0
0
0
1
OE
0
1
X
X
MODE
Read
Read
Write
Standby
I CC
Active
Active
Active
Standby
OUTPUTS
Active
High Impedance
High Impedance
High Impedance
X = Don’t care.
Read Mode
The DS2045W executes a read cycle whenever WE (write
enable) is inactive (high) and CE (chip enable) is active
(low). The unique address specified by the 17 address
inputs (A0 to A16) defines which of the 131,072 bytes of
data is to be accessed. Valid data will be available to the
eight data output drivers within t ACC (access time) after
the last address input signal is stable, providing that CE
and OE (output enable) access times are also satisfied. If
CE and OE access times are not satisfied, then data
access must be measured from the later occurring signal
( CE or OE ) and the limiting parameter is either t CO for CE
or t OE for OE rather than address access.
Write Mode
The DS2045W executes a write cycle whenever the CE
and WE signals are active (low) after address inputs
are stable. The later-occurring falling edge of CE or WE
will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE . All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t WR ) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output drivers have been enabled ( CE
and OE active) then WE will disable the outputs in t ODW
from its falling edge.
Data-Retention Mode
The DS2045W provides full functional capability for V CC
greater than 3.0V and write-protects by 2.8V. Data is
maintained in the absence of V CC without additional
support circuitry. The NV static RAM constantly moni-
tors V CC . Should the supply voltage decay, the NV
SRAM automatically write-protects itself. All inputs
become “don’t care”, and all data outputs become high
impedance. As V CC falls below approximately 2.5V
(V SW ), the power-switching circuit connects the lithium
energy source to the RAM to retain data. During power-
up, when V CC rises above V SW , the power-switching
circuit connects external V CC to the RAM and discon-
nects the lithium energy source. Normal RAM operation
can resume after V CC exceeds V TP for a minimum
duration of t REC .
Battery Charging
When V CC is greater than V TP , an internal regulator
charges the battery. The UL-approved charger circuit
includes short-circuit protection and a temperature-sta-
bilized voltage reference for on-demand charging of
the internal battery. Typical data-retention expectations
of 3 years per charge cycle are achievable.
A maximum of 96 hours of charging time is required to
fully charge a depleted battery.
System Power Monitoring
When the external V CC supply falls below the selected
out-of-tolerance trip point, the output RST is forced
active (low). Once active, the RST is held active until
the V CC supply has fallen below that of the internal bat-
tery. On power-up, the RST output is held active until
the external supply is greater than the selected trip
point and one reset timeout period (t RPU ) has elapsed.
This is sufficiently longer than t REC to ensure that the
SRAM is ready for access by the microprocessor.
Freshness Seal and Shipping
The DS2045W is shipped from Dallas Semiconductor
with the lithium battery electrically disconnected, guar-
anteeing that no battery capacity has been consumed
during transit or storage. As shipped, the lithium battery
is ~60% charged, and no preassembly charging oper-
ations should be attempted.
When V CC is first applied at a level greater than V TP ,
the lithium battery is enabled for backup operation. A
96 hour initial battery charge time is recommended for
new system installations.
10
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2045W-100# | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS2045Y | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Single-Piece 1Mb Nonvolatile SRAM |
| DS2045Y-100 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS2045Y-100# | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS2045Y20# | 制造商:Maxim Integrated Products 功能描述: |
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