参数资料
型号: DS2151QB
厂商: Maxim Integrated Products
文件页数: 58/60页
文件大小: 0K
描述: IC TXRX T1 1-CHIP 5V LP 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 26
功能: 单芯片收发器
接口: T1
电路数: 1
电源电压: 4.75 V ~ 5.25 V
电流 - 电源: 65mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 管件
包括: 警报检测器和发生器,CSU 回路代码发生器和检测器,DSX-1和CSU 线路补偿发生器
产品目录页面: 1429 (CN2011-ZH PDF)
DS2151Q
7 of 60
PIN
NAME
TYPE
FUNCTION
20
BTS
I
Bus Type Select. Strap high to select Motorola bus timing; strap low to select
Intel bus timing. This pin controls the function of the
RD(DS), ALE(AS), and
WR(R/W) pins. If BTS = 1, then these pins assume the function listed in
parentheses.
21, 22
RTIP,
RRING
Receive Tip and Ring. Analog inputs for clock recovery circuitry; connects
to a 1:1 transformer (see Section 13 for details).
23
RVDD
Receive Analog Positive Supply. 5.0V. Should be tied to DVDD and TVDD
pins.
24
RVSS
Receive Signal Ground. 0V. Should be tied to local ground plane.
25, 26
XTAL1,
XTAL2
Crystal Connections. A pullable 6.176MHz crystal must be applied to these
pins. See Section 13 for crystal specifications.
27
INT1
O
Receive Alarm Interrupt 1. Flags host controller during alarm conditions
defined in Status Register 1. Active low, open drain output.
28
INT2
O
Receive Alarm Interrupt 2. Flags host controller during conditions defined
in Status Register 2. Active low, open drain output.
29
TTIP
Transmit Tip. Analog line driver output; connects to a step-up transformer
(see Section 13 for details).
30
TVSS
Transmit Signal Ground. 0V. Should be tied to local ground plane.
31
TVDD
Transmit Analog Positive Supply. 5.0V. Should be tied to DVDD and
RVDD pins.
32
TRING
Transmit Ring. Analog line driver outputs; connects to a step-up transformer
(see Section 13 for details).
33
TCHBLK
O
Transmit Channel Block. A user-programmable output that can be forced
high or low during any of the 24 T1 channels. Useful for blocking clocks to a
serial UART or LAPD controller in applications where not all T1 channels are
used such as Fractional T1, 384kbps service, 768kbps, or ISDN-PRI. Also
useful for locating individual channels in drop-and-insert applications. See
Section 14 for timing details.
34
TLCLK
O
Transmit Link Clock. 4kHz or 2kHz (ZBTSI) demand clock for the TLINK
input. See Section 14 for timing details.
35
TLINK
I
Transmit Link Data. If enabled via TCR1.2, this pin will be sampled during
the F-bit time on the falling edge of TCLK for data insertion into either the
FDL stream (ESF) or the Fs bit position (D4) or the Z-bit position (ZBTSI).
See Section 14 for timing details.
36
TSYNC
I/O
Transmit Sync. A pulse at this pin will establish either frame or multiframe
boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can be programmed
to output either a frame or multiframe pulse at this pin. If this pin is set to
output pulses at frame boundaries, it can also be set via TCR2.4 to output
double-wide pulses at signaling frames. See Section 14 for timing details.
37
DVDD
Digital Positive Supply. 5.0V. Should be tied to RVDD and TVDD pins.
38
TCLK
I
Transmit Clock. 1.544MHz primary clock.
39
TSER
I
Transmit Serial Data. Transmit NRZ serial data, sampled on the falling edge
of TCLK.
40
TCHCLK
O
Transmit Channel Clock. 192kHz clock that pulses high during the LSB of
each channel. Useful for parallel to serial conversion of channel data, locating
robbed-bit signaling bits, and for blocking clocks in DDS applications. See
Section 14 for timing details.
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DS2151QB+ 功能描述:网络控制器与处理器 IC T1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS2151QB+T&R 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel