DS2153Q-A7+T&R (Maxim) PDF资料下载 Datasheet(10/60 页)

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型号：	DS2153Q-A7+T&R
厂商：	Maxim Integrated Products
文件页数：	10/60页
文件大小：	0K
描述：	IC TXRX E1 1-CHIP 5V 44-PLCC
产品培训模块：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
标准包装：	500
功能：	单芯片收发器
接口：	E1
电路数：	1
电源电压：	4.75 V ~ 5.25 V
电流 - 电源：	65mA
工作温度：	0°C ~ 70°C
安装类型：	表面贴装
封装/外壳：	44-LCC（J 形引线）
供应商设备封装：	44-PLCC（16.59x16.59）
包装：	带卷 (TR)

DS2153Q

18 of 60

5 STATUS AND INFORMATION REGISTERS

There is a set of four registers that contain information on the current real-time status of the DS2153Q:

Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer

Status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one

of these four registers will be set to a 1. All of the bits in these registers operate in a latched fashion

(except for the SSR). This means that if an event occurs and a bit is set to a 1 in any of the registers, it

will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set

again until the event has occurred again or if the alarm is still present.

The user will always precede a read of the SR1, SR2, and RIR registers with a write. The byte written to

the register will inform the DS2153Q which bits the user wishes to read and have cleared. The user will

write a byte to one of these three registers, with a 1 in the bit positions he or she wishes to read and a 0 in

the bit positions he or she does not wish to obtain the latest information on. When a 1 is written to a bit

location, the read register will be updated with current value and it will be cleared. When a 0 is written to

a bit position, the read register will not be updated and the previous value will be held. A write to the

status and information registers will be immediately followed by a read of the same register. The read

result should be logically ANDed with the mask byte that was just written and this value should be

written back into the same register to insure that bit does indeed clear. This second write step is necessary

because the alarms and events in the status registers occur asynchronously in respect to their access via

the parallel port. This write-read-write scheme allows an external microcontroller or microprocessor to

individually poll certain bits without disturbing the other bits in the register. This operation is key in

controlling the DS2153Q with higher-order software languages.

The SSR register operates differently than the other three. It is a read-only register and it reports the status

of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of

this register with a write.

The SR1 and SR2 registers have the unique ability to initiate a hardware interrupt via the INT1 and INT2

pins, respectively. Each of the alarms and events in the SR1 and SR2 can be either masked or unmasked

from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2),

respectively.

相关代理商/技术参数	参数描述
DS2153QN	制造商:未知厂家制造商全称:未知厂家功能描述:PCM Transceiver
DS2153QN-A5	功能描述:IC TXRX E1 1-CHIP 5V IND 44-PLCC RoHS:否类别:集成电路 (IC) >> 接口 - 电信系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:*
DS2153QN-A7	功能描述:网络控制器与处理器 IC RoHS:否制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS2153QN-A7/T&R	制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS2153QN-A7/T&R+	制造商:Maxim Integrated Products 功能描述:FRAMER E1/ISDN-PRI/PCM-30 5V 44PLCC - Tape and Reel

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