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参数资料
| 型号： | DS2153Q-A7+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 56/60页 |
| 文件大小： | 0K |
| 描述： | IC TXRX E1 1-CHIP 5V 44-PLCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 500 |
| 功能： | 单芯片收发器 |
| 接口： | E1 |
| 电路数： | 1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 电流 - 电源： | 65mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 带卷 (TR) |
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DS2153Q
6 of 60
2 PIN DESCRIPTION
PIN
NAME
TYPE
FUNCTION
1–4,
41–44
AD4–AD7,
AD0–AD3
I/O
Address/Data Bus. An 8-bit multiplexed address/data bus.
5
RD
(DS)
I
Active-Low Read Input (Data Strobe)
6
CS
I
Active-Low Chip Select. Must be low to read or write the port.
7
ALE(AS)
I
Address Latch Enable (Address Strobe). A positive going edge
serves to demultiplex the bus.
8
WR
(R/ W )
I
Active-Low Write Input (Read/Write)
9
RLINK
O
Receive Link Data. Outputs the full receive data stream including the
Sa bits. See Section 14 for timing details.
10
RLCLK
O
Receive Link Clock. 4kHz to 20kHz demand clock for the RLINK
output. Controlled by RCR2. See Section 14 for timing details.
11
DVSS
—
Digital Signal Ground. 0.0V. Should be tied to local ground plane.
12
RCLK
O
Receive Clock. Recovered 2.048MHz clock.
13
RCHCLK
O
Receive Channel Clock. 256kHz clock that pulses high during the
LSB of each channel. Useful for parallel to serial conversion of
channel data. See Section 14 for timing details.
14
RSER
O
Receive Serial Data. Received NRZ serial data, updated on rising
edges of RCLK or SYSCLK.
15
RSYNC
I/O
Receive Sync. An extracted pulse, one RCLK wide, is output at this
pin, which identifies either frame (RCR1.6 = 0) or multiframe
boundaries (RCR1.6 = 1). If the elastic store is enabled via the
RCR2.1, then this pin can be enabled to be an input via RCR1.5 at
which a frame boundary pulse is applied. See Section 14 for timing
details.
16
RLOS/LOTC
O
Receive Loss of Sync/Loss of Transmit Clock. A dual function
output. If TCR2.0 = 0, will toggle high when the synchronizer is
searching for the E1 frame and multiframe; if TCR2.0 = 1, will toggle
high if the TCLK pin has not toggled for 5
s.
17
SYSCLK
I
System Clock. 1.544MHz or 2.048MHz clock. Only used when the
elastic store functions are enabled via either RCR2.1. Should be tied
low in applications that do not use the elastic store. If tied high for at
least 100
s, will force all output pins (including the parallel port) to
tri-state.
18
RCHBLK
O
Receive Channel Block. A user-programmable output that can be
forced high or low during any of the 32 E1 channels. Useful for
blocking clocks to a serial UART or LAPD controller in applications
where not all E1 channels are used such as Fractional E1, 384kbps
service (H0), 1920kbps (H12), or ISDN-PRI. Also useful for locating
individual channels in drop-and-insert applications. See Section 14 for
timing details.
19
ACLKI
I
Alternate Clock Input. Upon a receive carrier loss, the clock applied
at this pin (normally 2.048MHz) will be routed to the RCLK pin. If no
clock is routed to this pin, then it should be tied to DVSS via a 1k
resistor.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2153QN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PCM Transceiver |
| DS2153QN-A5 | 功能描述:IC TXRX E1 1-CHIP 5V IND 44-PLCC RoHS:否 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| DS2153QN-A7 | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2153QN-A7/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS2153QN-A7/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER E1/ISDN-PRI/PCM-30 5V 44PLCC - Tape and Reel |
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