参数资料
型号: DS2153Q-A7+T&R
厂商: Maxim Integrated Products
文件页数: 37/60页
文件大小: 0K
描述: IC TXRX E1 1-CHIP 5V 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 500
功能: 单芯片收发器
接口: E1
电路数: 1
电源电压: 4.75 V ~ 5.25 V
电流 - 电源: 65mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 带卷 (TR)
DS2153Q
42 of 60
13.3 Jitter Attenuator
The DS2153Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications
where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications.
The characteristics of the attenuation are shown in Figure 13-4. The jitter attenuator can be placed in
either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR.
Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order
for the jitter attenuator to operate properly, a crystal with the specifications listed in Table 13-4 must be
connected to the XTAL1 and XTAL2 pins.
The jitter attenuator divides the clock provided by the 8.192MHz crystal at the XTAL1 and XTAL2 pins
to create an output clock that contains very little jitter. On-board circuitry will pull the crystal (by
switching in or out load capacitance) to keep it long-term averaged to the same frequency as the incoming
E1 signal. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth
is 32 bits), then the DS2153Q will divide the attached crystal by either 3.5 or 4.5 instead of the normal 4
to keep the buffer from overflowing. When the device divides by either 3.5 or 4.5, it also sets the Jitter
Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
Table 13-4. Crystal Selection Guidelines
PARAMETER
SPECIFICATION
Parallel Resonant Frequency
8.192MHz
Mode
Fundamental
Load Capacitance
18pF to 20pF (18.5pF nominal)
Tolerance
±50ppm
Pullability
CL = 10pF, delta frequency = +175ppm to
+250ppm
CL = 45pF, delta frequency = -175ppm to -250ppm
Effective Series Resistance
30
maximum
Crystal Cut
AT
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