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| 型号： | DS21552LN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 83/137页 |
| 文件大小： | 0K |
| 描述： | IC TXRX T1 1-CHIP 5V 100-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 功能： | 单芯片收发器 |
| 接口： | E1，HDLC，J1，T1 |
| 电路数： | 1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 电流 - 电源： | 75mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
| 包括： | DSX-1 和 CSU 线路补偿发生器，HDLC 控制器，带内回路代码发生器和检测器 |
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DS21352/DS21552
5 of 137
1. LIST OF FIGURES
Figure 3-1 SCT BLOCK DIAGRAM.........................................................................................................9
Figure 16-1 EXTERNAL ANALOG CONNECTIONS ..........................................................................87
Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS ..........................................................................88
Figure 16-3 TRANSMIT WAVEFORM TEMPLANE............................................................................89
Figure 16-4 JITTER TOLERANCE.........................................................................................................91
Figure 16-5 JITTER ATTENUATION ....................................................................................................91
Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552...........................................93
Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR TE DS21352..............................................94
Figure 16-8 TYPICAL MONITOR PORT APPLICATION....................................................................95
Figure 19-1 JTAG FUNCTIONAL BLOCK DIAGRAM......................................................................100
Figure 19-2 TAP CONTROLLER STATE DIAGRAM ........................................................................103
Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS ............................................................110
Figure 21-1 RECEIVE SIDE D4 TIMING.............................................................................................111
Figure 21-2 RECEIVE SIDE ESF TIMING...........................................................................................112
Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled)..............................113
Figure 21-4 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) ...........113
Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) ...........114
Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE ..............................115
Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE...........................116
Figure 21-8 TRANSMIT SIDE D4 TIMING.........................................................................................117
Figure 21-9 TRANSMIT SIDE ESF TIMING.......................................................................................118
Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) ........................119
Figure 21-11 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)......119
Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)......120
Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE.........................121
Figure 21-14 TRANSMIT SIDE INTERLEAVE BUS OPERATION, FRAME MODE .....................122
Figure 22-1 RECEIVE DATA FLOW ...................................................................................................123
Figure 22-2 TRANSMIT DATA FLOW................................................................................................124
Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX=1) .............................................................127
Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ...........................................................127
Figure 24-3 MOTOROLA BUS TIMING (BTS=1 / MUX=1)..............................................................128
Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX=0) ..............................................................130
Figure 24-5 INTEL BUS READ TIMING (BTS=0 / MUX=0) .............................................................130
Figure 24-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-7 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-8 RECEIVE SIDE TIMING ..................................................................................................133
Figure 24-9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED...............................................134
Figure 24-10 RECEIVE LINE INTERFACE TIMING .........................................................................135
Figure 24-11 TRANSMIT SIDE TIMING.............................................................................................137
Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED .........................................138
Figure 24-13 TRANSMIT LINE INTERFACE TIMING......................................................................138
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21552LN+ | 功能描述:网络控制器与处理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21554 | 制造商:Maxim Integrated Products 功能描述: |
| DS21554G | 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| DS21554GN | 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 电信 系列:- 产品培训模块:Lead (SnPb) Finish for COTS 产品变化通告:Product Discontinuation 06/Feb/2012 标准包装:750 系列:* |
| DS21554L | 功能描述:网络控制器与处理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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