参数资料
型号: DS21Q42T+
厂商: Maxim Integrated Products
文件页数: 44/116页
文件大小: 0K
描述: IC FRAMER ENHANCED T1 4X 128TQFP
标准包装: 72
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 管件
DS21Q42
33 of 116
CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)
(MSB)
LSB)
RESMDM TCLKSRC RLOSF
RSMS
PDE
ECUS
TLOOP
TESMDM
SYMBOL
POSITION
NAME AND DESCRIPTION
RESMDM
CCR3.7
Receive Elastic Store Minimum Delay Mode. See Section 13 for
details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
TCLKSRC
CCR3.6
Transmit Clock Source Select. This function allows the user to
internally select RCLK as the clock source for the transmit side
formatter.
0 = Transmit side formatter clocked with signal applied at TCLK
pin.
LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
RLOSF
CCR3.5
Function of the RLOS/LOTC Output. Active only when FMS =
1 (DS21Q41 emulation).
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
RSMS
CCR3.4
RSYNC Multiframe Skip Control. Useful in framing format
conversions from D4 to ESF. This function is not available when
the receive side elastic store is enabled.
0 = RSYNC will output a pulse at every multiframe
1 = RSYNC will output a pulse at every other multiframe note: for
this
bit to have any affect, the RSYNC must be set to output multiframe
pulses (RCR2.4=1 and RCR2.3=0).
PDE
CCR3.3
Pulse Density Enforcer Enable.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
ECUS
CCR3.2
Error Counter Update Select. See Section 8 for details.
0 = update error counters once a second
1 = update error counters every 42 ms (333 frames)
TLOOP
CCR3.1
Transmit Loop Code Enable. See Section 16 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as defined
in TCD register
TESMDM
CCR3.0
Transmit Elastic Store Minimum Delay Mode. See Section 13
for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
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