参数资料
型号: DS21Q42T+
厂商: Maxim Integrated Products
文件页数: 61/116页
文件大小: 0K
描述: IC FRAMER ENHANCED T1 4X 128TQFP
标准包装: 72
控制器类型: T1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 管件
DS21Q42
49 of 116
(MSB)
LSB)
B1
B2
B3
B4
B5
B6
B7
B8
SYMBOL
POSITION
NAME AND DESCRIPTION
B1
TDS0M.7
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be transmitted).
B2
TDS0M.6
Transmit DS0 Channel Bit 2.
B3
TDS0M.5
Transmit DS0 Channel Bit 3.
B4
TDS0M.4
Transmit DS0 Channel Bit 4.
B5
TDS0M.3
Transmit DS0 Channel Bit 5.
B6
TDS0M.2
Transmit DS0 Channel Bit 6.
B7
TDS0M.1
Transmit DS0 Channel Bit 7.
B8
TDS0M.0
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last
bit to be transmitted).
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
[repeated here from section 6 for convenience]
(MSB)
(LSB)
RJC
RESALGN
TESALGN
RCM4
RCM3
RCM2
RCM1
RCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
RJC
CCR6.7
Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal
operation)
1 = use Japanese standard JT–G704 CRC6 calculation
RESALGN
CCR6.6
Receive Elastic Store Align. Setting this bit from a zero to a
one will force the receive elastic store’s write/read pointers to
a minim separation of half a frame. If pointer separation is
already greater than half a frame, setting this bit will have no
effect. Should be toggled after RSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent
align. See Section 13 for details.
TESALGN
CCR6.5
Transmit Elastic Store Align. Setting this bit from a zero to
a one will force the transmit elastic store’s write/read pointers
to a minimum separation of half a frame. If pointer separation
is already greater than half a frame, setting this bit will have no
effect. Should be toggled after TSYSCLK has been applied
and is stable. Must be cleared and set again for a subsequent
align. See Section 13 for details.
RCM4
CCR6.4
Receive Channel Monitor Bit 4. MSB of a channel decode
that determines which receive channel data will appear in the
RDS0M register. See Section 9 for details.
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