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参数资料
型号： DS21Q44T+
厂商： Maxim Integrated Products
文件页数： 43/105页
文件大小： 0K
描述： IC FRAMER ENHANCED E1 4X 128TQFP
标准包装： 72
控制器类型： E1 调帧器
接口： 并行/串行
电源电压： 2.97 V ~ 3.63 V
电流 - 电源： 75mA
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 128-LQFP
供应商设备封装： 128-LQFP（14x20）
包装： 管件
DS21Q44
42 of 105
the framer should be programmed to count BPVs when receiving AMI code and to count CVs when
receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions.
The counter saturates at 65,535 and will not rollover. The bit error rate on a E1 line would have to be
greater than 10** –2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB)
(LSB)
V15
V14
V13
V12
V11
V10
V9
V8
VCR1
V7
V6
V5
V4
V3
V2
V1
V0
VCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
V15
VCR1.7
MSB of the 16–bit code violation count
V0
VCR2.0
LSB of the 10–bit code violation count
CRC4 Error Counter
CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant
word of a 10–bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the
maximum CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is
disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of
multiframe sync occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB)
(LSB)
(note 1)
CRC9
CRC8
CRCCR1
CRC7
CRC6
CRC5
CRC4
CRC3
CRC2
CRC1
CRC0
CRCCR2
SYMBOL
POSITION
NAME AND DESCRIPTION
CRC9
CRCCR1.1
MSB of the 10–Bit CRC4 error count
CRC0
CRCCR2.0
LSB of the 10–Bit CRC4 error count
NOTES:
1) The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12–bit FAS error
counter.
E-Bit Counter
E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10–bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E–bit is set to zero. Since the maximum E–bit count in a one second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
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