参数资料
型号: DS21Q44T+
厂商: Maxim Integrated Products
文件页数: 77/105页
文件大小: 0K
描述: IC FRAMER ENHANCED E1 4X 128TQFP
标准包装: 72
控制器类型: E1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 管件
DS21Q44
73 of 105
17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
17.1 Description
The DS21Q44 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP,
and IDCODE. See Figure 17-1 for a block diagram. The DS21Q44 contains the following items which
meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The JTAG feature is only available when the DS21Q44 feature set is selected (FMS = 0). The JTAG
feature is disabled when the DS21Q44 is configured for emulation of the DS21Q43 (FMS = 1).
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 17-1. BOUNDARY SCAN ARCHITECTURE
+V
Boundary Scan
Register
Identification
Register
Bypass
Register
Instruction
Register
JTDI
JTMS
JTCLK
JTRST
JTDO
+V
Test Access Port
Controller
MUX
10K
Select
Output Enable
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