参数资料
型号: DS21Q44T+
厂商: Maxim Integrated Products
文件页数: 63/105页
文件大小: 0K
描述: IC FRAMER ENHANCED E1 4X 128TQFP
标准包装: 72
控制器类型: E1 调帧器
接口: 并行/串行
电源电压: 2.97 V ~ 3.63 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-LQFP(14x20)
包装: 管件
DS21Q44
60 of 105
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa5
TSaCR.3
Additional Bit 5 Insertion Control Bit.
0=do not insert data from the TSa5 register into the transmit data
stream.
1=insert data from the TSa5 register into the transmit data
stream.
Sa6
TSaCR.2
Additional Bit 6 Insertion Control Bit.
0=do not insert data from the TSa6 register into the transmit data
stream.
1=insert data from the TSa6 register into the transmit data
stream.
Sa7
TSaCR.1
Additional Bit 7 Insertion Control Bit.
0=do not insert data from the TSa7 register into the transmit data
stream.
1=insert data from the TSa7 register into the transmit data
stream.
Sa8
TSaCR.0
Additional Bit 8 Insertion Control Bit.
0=do not insert data from the TSa8 register into the transmit data
stream.
1=insert data from the TSa8 register into the transmit data
stream.
15. HDLC CONTROLLER FOR THE SA BITS OR DS0
Each framer in the DS21Q44 has the ability to extract/insert data from/ into the Sa bit positions (Sa4 to
Sa8) or from/to any multiple of DS0 channels Each framer contains a complete HDLC controller and this
operation is covered in Section 15.1.
15.1 General Overview
Each framer contains a complete HDLC controller with 64–byte buffers in both the transmit and receive
directions. The HDLC controller performs all the necessary overhead for generating and receiving a
HDLC formatted message.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to
the HDLC data stream.
There are eleven registers that the host will use to operate and control the operation of the HDLC
controller. A brief description of the registers is shown in Table 15-1.
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