参数资料
型号: DS2790G+T&R
厂商: Maxim Integrated Products
文件页数: 13/41页
文件大小: 0K
描述: IC FUEL GAUGE BATT 28-TDFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
功能: 燃料,电量检测计/监控器
电池化学: 锂离子(Li-Ion)
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-TDFN
供应商设备封装: 28-TDFN-EP(8x4)
包装: 带卷 (TR)
DS2790 Programmable 1-Cell Li-Ion Fuel Gauge and Protector
SYSTEM RESET
Several reset sources are provided for microcontroller control. Although code execution is halted in the reset state,
OSCI continues to run.
Power-On Reset - An internal power-on reset circuit enhances system reliability. This circuit forces the device to
perform a power-on reset whenever a rising voltage on V DD climbs above V POR . At this point the following events
occur:
?
?
?
All registers and circuits enter their reset state,
The POR flag (WDCN.7) is set to indicate the source of the reset,
Code execution begins at location 8000h
Watchdog Timer Reset - A few differences exist between the watchdog timer in the DS2790 and the one
described in the MAXQ Family User's Guide as described in the Watchdog Timer section. Software can determine
if a reset is caused by a watchdog timeout by checking the Watchdog Timer Reset Flag (WTRF) in the WDCN
register. Execution resumes at location 8000h following a watchdog timer reset.
External System Reset - Asserting the external RST (port P0.2) pin low causes the device to enter the reset state.
The external reset function is described in the MAXQ Family User's Guide . Execution resumes at location 8000h
after the RST pin is released.
MAXQ20 CORE POWER MANAGEMENT
The DS2790 is designed for low power battery monitoring applications. The peripherals have been designed with
the ability to wake the processor from Stop mode any time software intervention is needed. Power management is
optimized in the applications by performing any necessary processing as quickly as possible, and re-entering the
low power Stop mode. Processing resumes from stop mode via any of the following sources (when enabled):
?
?
?
?
An external interrupt is triggered.
An external reset signal is applied to the RST pin.
A Watchdog Timer interrupt occurs.
An internal interrupt event occurs.
No division of the internal system clock is supported, subsequently the PMME and CD[1:0] bits described in the
MAXQ users guide are not implemented in the DS2790.
WATCHDOG TIMER
The watchdog timer provides a mechanism to reset the processor in the case of undesirable code execution. The
watchdog timer is a hardware timer designed to be periodically reset by the application software. If the software
operates correctly, the timer is reset before it reaches its maximum count. However, if undesireable code execution
prevents a reset of the watchdog timer, the timer reaches its maximum count and resets the processor.
The watchdog timer in the DS2790 differs in two respects from the one described in the MAXQ Family User's
Guide : 1) the clock used by the timer is the 70kHz OSCA clock that runs independently of the 1MHz OSCI (or
system) clock, and 2) the watchdog interrupt is an asynchronous interrupt that can bring the processor out of stop
mode.
The watchdog timer is controlled through bits in the WDCN register. Its timeout period can be set to one of the four
programmable intervals ranging from 2 12 to 2 21 OSCA clock periods (59ms up to 30s). The watchdog interrupt
occurs at the end of this timeout period, which is 512 OSCA clock periods, or 7.3ms, before the reset.
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