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参数资料
| 型号： | DS2790G+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 5/41页 |
| 文件大小： | 0K |
| 描述： | IC FUEL GAUGE BATT 28-TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 燃料，电量检测计/监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TDFN |
| 供应商设备封装： | 28-TDFN-EP（8x4） |
| 包装： | 带卷 (TR) |
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DS2790 Programmable 1-Cell Li-Ion Fuel Gauge and Protector
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Setup Time for STOP
Condition
t SU:STO
0.6
μs
Spike Pulse Width that can be
Suppressed by Input Filter
Clock Low Time-Out
Cumulative Clock Low Extend
Time for Slave Device
Cumulative Clock Low Extend
Time for Bus Master
SCL, SDA Input Capacitance
t SP
t TIMEOUT
t LOW:SEXT
t LOW:MEXT
C BIN
(Note 10)
TTO_DIS = 0,
(Note 11)
TLS_DIS = 0,
(Note 12)
TTO_DIS = 0,
TLS_DIS = 0
(Note 13)
0
25
50
35
25
10
60
ns
ms
ms
ms
pF
ELECTRICAL CHARACTERISTICS: JTAG INTERFACE
(2.5V ≤ V DD ≤ 5.5V, T A = -20 ° C to +70 ° C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
JTAG Logic Reference
TCK High Time
TCK Low Time
TCK Low to TDO Output
TMS, TDI Input Setup to TCK
High
TMS, TDI Input Hold after TCK
High
V REF
t TH
t TL
t TLQ
t DVTH
t THDX
4.0
4.0
1.0
4.0
V DD ÷ 2
1.0
V
μs
μs
μs
μs
μs
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Maximum current assumuing 100% CPU duty cycle.
This value does not include current in SDA, SCL, and P0.0–P0.5.
All Voltages referenced to V SS .
Voltage register can report up to 4.992V, however VIN pin input saturation occurs at 4.75V minimum.
The secondary short circuit delay is measured from the falling transition on V DD to the resultant falling transition on DC. The delay
is measured from the time V DD reaches V POR - 0.5V to the time DC reaches 50% of V CP (4.5V).
f SCL must meet the minimum clock low time plus the rise/fall times.
The maximum t HD:DAT has only to be met if the device does not stretch the LOW period (t LOW ) of the SCL signal.
This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL.
C B ? total capacitance of one bus line in pF.
Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Devices participating in data transfer will timeout when any clock low exceeds the minimum t TIMEOUT of 25ms. Devices that have
detected a timeout condition must reset the communication no later than the maximum t TIMEOUT of 35ms. The maximum value
specified must be adhered to by both devices as it incorporates the cumulative stretch limit for the master (10ms) and slave
device (25ms).
t LOW:SEXT is the cumulative time the slave is allowed to extend the clock from the initial START to the STOP. If the DS2790
exceeds this time, it will release both SDA and SCL and reset the communication interface.
t LOW:MEXT is the cumulative time the master is allowed to extend the clock cycles within each byte of a communication sequence. If
the bus master exceeds this time it is possible for the DS2790 to violate t TIMEOUT without having violated t LOW:SEXT .
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